Boundary clock window determination method, circuit and terminal equipment and storage medium

Abstract

The invention discloses a boundary clock window determination method. The method comprises the following steps: dynamic clock configuration: enabling an FPGA to initialize dynamic clock configurationaccording to a dynamic configuration command; training data transmission: enabling a CPU to query clock locking state information of the FPGA and transmit training data to the FPGA; phase cycle section testing: traversing the whole phase cycle section to perform dynamic clock configuration and transmission training; and clock window determination: obtaining a transmission correctness test result returned by the FPGA, and re-initiating clock locking according to the test result to complete clock window determination. Dynamic configuration of clock phases is completed by utilizing dynamic configuration interfaces of clock resources, such as PLL provided by the FPGA in cooperation with simple software and hardware logic functions. The design is simple, and certain self-adaptability is achieved. The method has a deserved value when the clock window of the medium-low speed parallel inter-chip interconnection bus is determined.

Description

technical field [0001] The invention relates to the field of clock window determination, in particular to a boundary clock window determination method, circuit, terminal equipment and storage medium. Background technique [0002] There are a large number of parallel synchronous bus interconnections in embedded systems, including between embedded CPU and peripherals, between FPGA and FPGA, and between FPGA and embedded CPU. Interconnection channels that support the interaction of these chip-level units all have the need to determine the clock window. like figure 1 As shown, sampling Data when the clock Clk is at point A is at the Tsetup boundary, and sampling Data when the clock Clk is at point B is at the Tholdon boundary. That is, when Clk is in any position between A and B, Data can be sampled reliably, so the window between A and B is the best window of Clk. [0003] In the actual project design, the determination of points A and B has a great relationship with the ado...

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