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Low-delay PCIE DMA data transmission method and controller

A data transmission method and low-latency technology, applied in the field of low-latency PCIEDMA data transmission methods and controllers, can solve the problems of long delay and time extension of read operations, and achieve the effects of optimizing data bandwidth, low latency, and reducing the number of TLPs

Active Publication Date: 2020-06-02
杭州熠芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In the above operation, multiple PCIE write and read operations are involved. Due to the long delay of the read operation on the PCIE bus (ms level), the delay in completing the entire operation is very long

Method used

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  • Low-delay PCIE DMA data transmission method and controller
  • Low-delay PCIE DMA data transmission method and controller
  • Low-delay PCIE DMA data transmission method and controller

Examples

Experimental program
Comparison scheme
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Embodiment 1

[0039] see figure 2 , image 3 , the present invention provides a low-latency PCIE DMA data transmission method, including an initiating device and a receiving device, a data window and a control window are mapped on the PCIE address space of the receiving device, and the data window is a segment of consecutive addresses on the receiving device PCIE memory space, the control window is a PCIE memory space with a continuous address on the receiving device; the data transmission steps between the initiating device and the receiving device include:

[0040] S1. The initiating device checks the status of the data window, and if there is enough space, writes data to the data window;

[0041] Specifically, when the initiating device writes data into the data window of the receiving device in order of addresses, the data window can accommodate multiple data blocks at the same time.

[0042] S2. The initiating device checks the status of the control window, and if there is enough sp...

Embodiment 2

[0054] see Figure 5 , the present embodiment provides a low-latency PCIE DMA controller, including a sending DMA device and a receiving DMA device, characterized in that: the sending DMA device and the receiving DMA device are connected through the PCIE bus to complete data transfer from the sending device to the receiving device transmission of

[0055] The receiving DMA device is used to map a data window and a control window on the PCIE address space, monitor and send to the PCIE write TLP of the control window, read the control symbol and process the transmitted data, and send the release control window space to the initiating device Notice;

[0056] The sending DMA device is used to maintain the state of the data window and the state of the control window; when transmitting data, check the state of the data window, if there is enough space, write data to the data window; check the state of the control window, if there is enough space, write the control window to the co...

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PUM

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Abstract

The invention provides a low-delay PCIE DMA data transmission method and a controller. The low-delay PCIE DMA data transmission method comprises an initiating device and a receiving device, a data window and a control window are mapped on a PCIE address space of the receiving device, and the data transmission step comprises the steps of S1, checking the state of the data window by the initiating device, and if enough space exists, data is written into the data window; S2, checking the state of the control window by the initiating device, and writing a control character to the control window ifthere is enough space; S3, receiving a write-in operation of the equipment monitoring control window, reading the control character and processing the transmitted data; S4, after the receiving deviceprocesses the control symbol, sending a notification of releasing the control window space to the initiating device; S5, after the receiving device processes the data, sending a notification of releasing the data window space to the initiating device; and S6, updating the data window state and the control window state by the initiating device according to the received notification of releasing the window space.

Description

technical field [0001] The invention belongs to direct memory access (DMA, Direct Memory Access) technology, in particular to a low-delay PCIE DMA data transmission method and a controller. Background technique [0002] The DMA controller can move data from one address space to another, and the transfer action itself is performed and completed by the DMA controller. The traditional DMA operation is that when there is data to be transmitted, the sending device notifies the receiving device to read the data, see figure 1 ,details as follows: [0003] 1. The sending device establishes a circular control character queue in its own address space. [0004] 2. When there is data to be transmitted, put the control character into the buffer queue, and the control character contains the position and length information of the data. [0005] 3. The sending device notifies the receiving device that there is a new control symbol in the buffer queue. [0006] 4. The receiving device re...

Claims

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Application Information

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IPC IPC(8): G06F13/28G06F13/42
CPCG06F13/28G06F13/4221G06F2213/0026
Inventor 张宇弘
Owner 杭州熠芯科技有限公司