Method for reading data and memory controller

Abstract

Provided are a data reading method and DDR controller. The method comprises: reading a first data corresponding to a first reading request from the DDR and continuing to read the adjacent data with an address neighboring to the address of the first data after receiving the first reading request sent by a central processing unit, the sum of the data volume of the first data and the adjacent data is the cache line capacity of the central processing unit; caching the adjacent data; reading a subsequent reading request of the adjacent data according to the received request, and sending the cached adjacent data to the central processing unit. The technical solution, relating to the field of computer, is mainly applied to computer systems, and capable of reducing the time required for a central processing unit to obtain the data of a complete cache line and improving the data processing efficiency of a computer system.

Description

Technical field [0001] The present invention relates to the field of computers, in particular to a method for reading data and a memory controller. Background technique [0002] In a computer system, a central processing unit (Central Processing Unit, CPU) sends data operation instructions to a memory controller (DDR Controller) to read data from the memory or write data to the memory. The memory controller puts the received data operation instructions into its own buffer queue and reorders it. The sorting principle is: the data operation instructions that make the accessed memory address close (in the same storage bank or the same address row) are arranged in sequence, so that data reading can be performed sequentially, avoiding the time caused by frequent switching of BANK (storage area) and address rows delay. The data in the memory is read out and loaded into the data response message, which is sent by the memory controller to the CACHE (high speed buffer memory) of the cen...

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Problems solved by technology

[0004] In the process of realizing the above-mentioned technical solution, the inventor found that the prior art has at least the following problems: multiple data manipulation instructions corresponding to the CACHE row capacity require that the memory addresses for reading data are usually continuous, and when reading data from the memory No need to switch BANK or address line frequently

However, in practical applications, when arriving at the cache queue of the memory controller, other data operation instructions may be inserted into the plurality of data operation instructions corresponding to the capacity of the CACHE row, especially when multi-central processing units and multi-memory cascade In a high-performance computer system composed of extensions (such as figure 1 As shown), different CPUs take different times to access different memories, and the routing schemes are different, which makes it more obvious that other data manipulation instructions are inserted into multiple consecutive data manipulation instructions corresponding to the same CACHE line, which makes the corresponding Among the multiple data operation instructions of the CACHE row, the data operation instructions that arrive later cannot enter the cache queue, and cannot be timed optimized, thus increasing the time it takes for the central processor to obtain a complete cache row of data, reducing the system processing efficiency

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