Antenna data interleaving and de-interleaving method based on FPGA

An antenna data and de-interleaving technology, applied in the field of FPGA-based antenna data interleaving and de-interleaving, can solve the problem of consuming large RAM resources and so on

Pending Publication Date: 2020-06-05
WUHAN HONGXIN TECH DEV CO LTD
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0009] The disadvantage of the ping-pong cache is that it needs to use twice the amount of RAM resources as the amount of antenna data
As the number of ante

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  • Antenna data interleaving and de-interleaving method based on FPGA
  • Antenna data interleaving and de-interleaving method based on FPGA
  • Antenna data interleaving and de-interleaving method based on FPGA

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Embodiment Construction

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

[0046] Provide a kind of FPGA-based antenna data interleaving and deinterleaving method in one embodiment of the present invention, this method comprises:

[0047]A write address exchange unit is set between the external write address and the write address of the DPRAM, and a read address exchange unit is set between the read address of the DPRAM and the external read address, and the DPRAM is located in the FPGA;

[0048] The write address of the DPARM is shifted by the write address switching unit, and t...

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Abstract

The embodiment of the invention provides an antenna data interleaving and de-interleaving method based on an FPGA. The method comprises the following steps: a write address exchange unit is arranged between an external write address and a write address of a DPRAM, a read address exchange unit is arranged between a read address of the DPRAM and an external read address, and the DPRAM is located inan FPGA; the write address of the DPARM is shifted through the write address switching unit, and the read address of the DPARM is shifted through the read address switching unit, so that the write address of the DPRAM in the current OFDM symbol period is the same as the read address of the DPRAM in the previous OFDM symbol period. According to the embodiment of the invention, the conversion of theread and write addresses of the DPRAM is controlled by the address exchange units, and the antenna interleaving and de-interleaving functions can be completed only by RAM resources with the same datavolume as the antenna, so that the RAM resources are saved.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to an FPGA-based antenna data interleaving and deinterleaving method. Background technique [0002] In the 4G / 5G wireless communication system, OFDM (Orthogonal Frequency Division Multiplexing, Orthogonal Frequency Division Multiplexing) is adopted, and its modulation and demodulation are realized based on the inverse Fourier transform IFFT and Fourier transform FFT respectively. FFT / IFFT in 4G / 5G wireless communication is converted based on one OFDM symbol. [0003] The data format transmitted from the IF side of the communication system to the baseband side is usually interleaved by antenna. For example, the interleaved data of 4 antennas is antenna 0 data 1 / antenna 1 data 1 / antenna 2 data 1 / antenna 3 data 1~antenna 0 data N / antenna 1 data N / antenna 2 data N / antenna 3 data N. Therefore, it is necessary to complete the deinterleaving of antenna interleaving dat...

Claims

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Application Information

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IPC IPC(8): H03M13/27G06F15/78
CPCH03M13/2703H03M13/2782G06F15/781Y02D30/70
Inventor 苏岚魏恒
Owner WUHAN HONGXIN TECH DEV CO LTD
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