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Matrix multiplication processor based on systolic array and data processing method thereof

A technology of pulsating array and matrix multiplication, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problem of high wiring complexity

Pending Publication Date: 2020-06-16
NANJING UNIV
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Problems solved by technology

[0005] In order to solve the technical problem of high wiring complexity of the matrix multiplication processor due to the large number of control signals, the application discloses a systolic array-based matrix multiplication processor and its data processing method through the following embodiments

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  • Matrix multiplication processor based on systolic array and data processing method thereof
  • Matrix multiplication processor based on systolic array and data processing method thereof
  • Matrix multiplication processor based on systolic array and data processing method thereof

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Embodiment Construction

[0041] In order to solve the technical problem of high wiring complexity of the matrix multiplication processor due to the large number of control signals, the present application discloses a systolic array-based matrix multiplication processor and a data processing method thereof through the following embodiments.

[0042] see figure 1 , a systolic array-based matrix multiplication processor disclosed in the first embodiment of the present application, including:

[0043] A systolic array composed of multiple basic computing units (Cells). The systolic array is composed of N*M basic computing units. The dimension of the systolic array can be configured, and the number of rows N can be greater than, less than or equal to The number of columns M. In the systolic array, any two adjacent basic operation units in each column are connected through a D flip-flop, and the D flip-flop is used for storing and transmitting data according to a clock signal. In an implementation manner,...

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Abstract

The invention discloses a matrix multiplication processor based on a systolic array and a data processing method thereof. The matrix multiplication processor comprises a pulsation array formed by arranging a plurality of basic operation units, a plurality of weight input channels and data input channels, any two adjacent basic operation units of each column in the pulsation array are connected through a D trigger; the D trigger is used for storing and transmitting data according to the clock signal; and the weight input channel and the data input channel are respectively used for inputting weight data into each basic operation unit in the corresponding row and inputting activation data into a data input interface of each column of bottom-end basic operation units in the pulsation array according to a clock signal. When the weight data and the activation data are broadcasted under the control of the clock signal, the D trigger can store and transmit the data at the same time without extra control signals, the number of the control signals is effectively reduced, and the wiring complexity of the matrix multiplication processor is reduced.

Description

technical field [0001] The present application relates to the technical fields of integrated circuits and communications, and in particular to a systolic array-based matrix multiplication processor and a data processing method thereof. Background technique [0002] A neural network model usually includes a large number of network layers, and each network layer has a convolution operation between a weight matrix and an activation matrix, wherein the weight matrix contains a large amount of weight data, and the activation matrix contains a large amount of activation data. When performing a convolution operation, the convolution operation is generally converted into a matrix multiplication, and then the matrix multiplication processor is used for calculation to obtain the result of the convolution operation. [0003] A matrix multiplication processor usually includes a plurality of basic operation units arranged in a systolic array, multiple weight data and activation data are ...

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Application Information

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IPC IPC(8): G06F17/16G06F7/523
CPCG06F17/16G06F7/523Y02D10/00
Inventor 王中风徐铭阳林军
Owner NANJING UNIV
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