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Formalized verification system

A technology of formal verification and formal description, applied in the field of formal verification, it can solve the problems of not covering all states of SEDS, and unable to guarantee the correctness and reliability of software.

Active Publication Date: 2020-06-26
EAST CHINA NORMAL UNIV
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Problems solved by technology

However, the test method can only test whether the functional logic of SEDS is correct by way of enumeration, and cannot cover all states of SEDS, so the correctness and reliability of the software cannot be guaranteed

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Embodiment Construction

[0023] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0024] The present invention adopts formal verification technology to accurately check the functional logic of SEDS to ensure the correctness and reliability of the software.

[0025] Based on this, the present invention proposes a formal verification system for SEDS functional logic check, which can run on electronic equipment (such as PC).

[0026] figure 1 The structural diagram of the formal verification system proposed for th...

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Abstract

The invention discloses a formal verification system, which comprises an SEDS modeling module used for establishing an SEDS model according to an electronic data form specification file; the model conversion module is used for converting the SEDS model into a formalized model suitable for model inspection; the property specification module is used for formally describing the property of the functional logic of the SEDS model; and the formal verification module is used for performing formal verification on the formal model and the described functional logic properties to obtain a verification result. According to the invention, the SEDS model is converted into the formalized model; formalized description is carried out on the property of the functional logic of the SEDS model; according tothe method, the formal model and the property description are subjected to formal verification, so that the functional logic of the SEDS is checked from the perspective of mathematical reasoning, thecorrectness and reliability of software are further guaranteed, Meanwhile, a user can discover conflicts or defects existing in the functional logic according to a verification result and correct errors in the SEDS model.

Description

technical field [0001] The invention mainly relates to the field of formal verification, in particular to a formal verification system. Background technique [0002] With the continuous adjustment of military strategy and the continuous advancement of aerospace technology, SEDS (Space Electronic DataSheet, electronic data sheet) has become the focus of work in the field of SOIS (spacecraft onboard interface services, spacecraft onboard interface services). In response to the needs of rapid integration and testing of spaceborne software currently implemented, SEDS can automatically generate spaceborne software, test cases and related documents through tools, thereby reducing the time for spaceborne software integration, testing, and maintenance, and ensuring data integrity in each development stage. Consistency, and once SEDS is formed, its application usually runs through all stages of project development and operation. Therefore, the functional logic consistency and comple...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
CPCG06F11/3608
Inventor 黄滟鸿杨秀丽史建琦曹桂涛郭欣
Owner EAST CHINA NORMAL UNIV
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