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Full-voltage ESD structure and implementation method

A technology of contact structure and isolation structure, which is applied in the direction of electrical components, transistors, electric solid devices, etc., can solve the problems of inability to realize ESD protection, ESD device breakdown failure, and inability to use ESD protection, so as to avoid design costs and process processing cost, increase applicable scenarios, and increase the effect of working voltage

Pending Publication Date: 2020-07-03
伟芯科技(绍兴)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The above traditional structure can meet the ESD protection requirements of some circuits, but if the circuit port needs to be used when the working voltage exceeds the normal voltage of the device, the above structure cannot be used for ESD protection of the circuit, otherwise ESD will be caused when the circuit is working normally The breakdown of the device fails, let alone the function of ESD protection

Method used

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  • Full-voltage ESD structure and implementation method
  • Full-voltage ESD structure and implementation method
  • Full-voltage ESD structure and implementation method

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Embodiment 1

[0035] An all-voltage ESD structure, including a MOS device used to form an ESD circuit, the MOS device includes a substrate, a polycrystalline gate formed on the substrate, and doped source regions and doped drain regions on both sides of the gate The doped source region and the doped drain region are respectively connected with a contact hole; wherein, a lightly doped structure is added between the periphery of the doped drain region of the MOS device and the substrate, or the doped drain region of the MOS device An isolation structure or an extension region is added between the heterodrain region and its channel; the lightly doped structure is a doped structure layer with a doping concentration lower than that of the same-type substrate or the same-type doped drain region.

[0036] The invention optimizes the device design structure by changing the contact structure between the drain region and the substrate of the original MOS device, or the structure between the drain regi...

Embodiment 2

[0052] The invention provides a method for realizing a full-voltage ESD structure, which includes: adding a lightly doped structure between the periphery of the doped drain region and the substrate for the MOS device used to form the ESD circuit, or the doped structure of the MOS device An isolation structure or an extension region is added between the heterodrain region and its channel; wherein the lightly doped structure is a doped structure layer with a doping concentration lower than that of the same-type substrate or the same-type doped drain region.

[0053] The MOS device in the present invention includes a substrate, a polycrystalline gate formed on the substrate, and a doped source region and a doped drain region on both sides of the gate; a doped source region and a doped drain The regions are respectively communicated with a contact hole. By improving the structure between the doped drain region and the substrate or channel, changing the contact structure between th...

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Abstract

The invention discloses a full-voltage ESD structure, which comprises an MOS device used for forming an ESD circuit. The MOS device comprises a substrate, a polycrystalline gate formed on the substrate, and a doped source region and a doped drain region which are arranged at two sides of the gate. The doped source region and the doped drain region are respectively communicated with a contact hole.A lightly doped structure is additionally arranged between the periphery of a doped drain region of the MOS device and a substrate, or an isolation structure or an extension region is additionally arranged between the doped drain region of the MOS device and a channel of the MOS device. The lightly doped structure is a doped structure layer of which the doping concentration is smaller than that of a homotype substrate or a homotype doped drain region. Under the condition enough ESD protection capability is guaranteed, the MOS device forming the ESD circuit is improved in various modes, so that the working voltage of a circuit port can be increased, the increase of design cost and process processing cost is avoided, the voltage application range of the ESD structure is expanded, the requirement that the voltage of the circuit port is higher than the working voltage of a normal device is met, and the application range is wide.

Description

technical field [0001] The invention relates to the technical field of electrostatic protection, in particular to a full-voltage ESD structure and a realization method. Background technique [0002] Integrated circuits (chips) and all electronic systems require electrostatic (Electro-Static discharge, ESD) protection design; in the current traditional technology, the power supply of integrated circuits or ESD protection of I / O is usually composed of NMOS devices or PMOS devices. Taking NMOS devices as an example, conventional devices are symmetrically N-type doped on a P substrate to form an NMOS device, such as Picture 1-1 ;Considering the ESD protection requirements, it is usually necessary to increase the length of the N-doped drain, and to form a metal silicide barrier layer on the drain, so as to improve the ESD conduction uniformity and ESD protection capability of the device, such as Figure 1-2 . [0003] The above traditional structure can meet the ESD protection ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L29/78
CPCH01L27/0266H01L29/7833H01L29/7835
Inventor 马树永
Owner 伟芯科技(绍兴)有限公司