141results about How to "Extended voltage range" patented technology

A memory cell includes a magnetic cell junction having an antiferromagnetic layer within a portion of the cell junction that is adapted to characterize a logic state of a bit written to the junction. More specifically, a memory cell includes, an antiferromagnetic layer arranged in contact with an adjacent magnetic layer within a storing portion of a magnetic cell junction. Such a magnetic cell junction configuration and a method for programming a memory cell with such a cell junction configuration may be used to improve the write selectivity of a memory cell array and reduce the amount of current needed to write a bit to a memory cell. Moreover, a memory cell includes a magnetic cell junction having an aspect ratio less than 1.6. In addition, a memory cell includes at least two resistors.

A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n⁻ Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

The invention discloses a reference voltage regulating circuit of an integrated circuit. A reference voltage system of the integrated circuit comprises an LDO module, a regulation module and a regulation control module. The regulation module comprises a first-stage calibration and regulation module and a second-stage calculation and regulation module. The regulation control module is connected with an off-chip program control module, a regulation control signal is generated according to a calibration signal provided by the program control module, the first-stage calibration and regulation module conducts first-stage calibration on reference voltage of the integrated circuit according to the regulation control signal, the second-stage calibration and regulation module conducts second-stage calibration on the basis of first-stage calibration according to the regulation control signal, the reference voltage is regulated to preset reference voltage, and accordingly the voltage range and precision of reference voltage regulation are effectively improved through two stages of calibration. The invention further discloses a reference voltage regulation system of the integrated circuit. The reference voltage regulating system comprises the reference voltage regulation circuit and the off-chip program control module.

The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further includes a first switching stage and a second switching stage and each stage has a P-type transistor and a N-type transistor to expand the range of the switching voltages such that the improvement of the pixel control is further enhanced. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

A bi-directional DC/DC converter comprises bridge circuits connected to DC voltage sources, an isolation transformer, an LC resonance circuit, and detection circuits for detecting voltages and currents of the DC voltage sources. A control circuit in the power flow from a first DC voltage source to a second DC voltage source changes over between fixed frequency control and frequency modulation control according to the magnitude of a control variable, and a control circuit in the power flow from a second DC voltage source to the first DC voltage source changes over between fixed frequency control and frequency modulation control according to the magnitude of another control variable. Thus, the bi-directional DC/DC converter can be applied to devices with a wide range of input and output voltages.

A memory circuit includes a plurality of memory cells and a plurality of bit lines and row lines connected to the memory cells for accessing selected memory cells. The memory circuit includes a programmable voltage source adapted for connection to at least one bit line and operative to precharge the bit line to a prescribed voltage level prior to accessing a selected one of the memory cells coupled to the bit line. A control circuit coupled to the bit line is operative to oppose discharge of the bit line during at least a portion of a given memory read cycle. A tracking circuit connected to the control circuit is operative to control a delay in activation of the control circuit and/or a duration of time the control circuit is active as a function of a parameter affecting signal development time of a data signal on the bit line.

An amplifier (100) comprises an input port (102) for receiving an input signal, an envelope port (104) for receiving an envelope signal indicative of an envelope of the input signal. The amplifier has a first transistor (M1) and a second transistor (M2). A first biasing circuit (120) is coupled to the envelope port (104) and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage (140) is coupled to the input port (102) for receiving the input signal, coupled to the first biasing circuit (120) for receiving the first bias voltage, coupled to a gate (g) of the first transistor (M1). A second biasing circuit (130) is coupled between the envelope port (104) and a gate (g ₂) of the second transistor (M2), and is arranged to generate a second bias voltage dependent on the envelope signal.

The present invention discloses a pixel display configuration by providing a voltage controller in each pixel control circuit for controlling the voltage inputted to the pixel electrodes. The controller includes a function of multiplexing the voltage input to the pixel electrodes and also a bit buffering and decoupling function to decouple and flexible change the input voltage level to the pixel electrodes. The controller further a delay element connected to the first and second switching stages for delaying a turning on of one stage after a turning off of another stage with sufficient delay for loading a predefined set of display data for preventing turning on of both said first and second switching stages. The rate of DC balancing can be increased to one KHz and higher to mitigate the possibility of DC offset effects and the image sticking problems caused by slow DC balancing rates. This invention further discloses an enabling technology for switching from one DC balance state to another without rewriting the data onto the panels. Therefore, it is not required to implement a high voltage CMOS designs and standard CMOS technologies can be applied to manufacture the storage cells and control panel for the LCOS displays with lower production cost and higher yields.

A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.

Disclosed are current sink and source circuits, a charge pump that incorporates them, and a phase locked loop that incorporates the charge pump. The current sink and source circuits each have a current mirror that biases a transistor connected to an output node. These circuits each further have a two-stage feedback amplifier to sense the current mirror drain voltage and to control the transistor gate voltage in order to stabilize the current mirror drain voltage independent of output voltage at the output node. The amplifier also increases output resistance at the output node. This configuration allows for a wide operation voltage range and ensures good circuit performance under a very low power supply. A charge pump that incorporates these circuits generates highly matched charging and discharging currents. A PLL that incorporates this charge pump exhibits minimal bandwidth shifts and minimal locking speed and jitter performance degradation.

A capacitive load driving circuit that drives a capacitive load, includes: a power supply unit that generates different voltages; a plurality of charge storage elements that are charged with the different voltages generated by the power supply unit; and a load driving section that connects a charge storage element arbitrarily selected from the plurality of charge storage elements to the capacitive load to drive the capacitive load, and connects, when at least two of the charge storage elements are selected, the at least two charge storage elements to the capacitive load in a state where the at least two charge storage elements are connected in series.

The invention provides a preparation method and application of a ZnCo2O4@MnO core-shell heterostructure nanotube array material. According to the prepared product, a ZnCo2O4 nanowire serves as a framework and is wrapped with a MnO nanofilm material, and the product grows vertically, is arranged orderly and has a regular three-dimensional heterostructure. Compared with the prior art, the product prepared through the preparation method is high in purity, good in dispersity, good and controllable in crystalline form, low in production cost and good in reproducibility. The prepared tubular ZnCo2O4@MnO core-shell heterostructure nanotube array grows on nickel foam, can serve as an electrode material of a super capacitor directly, has long-term circulatory stability, large specific capacitance and high energy density and power density, and has great commercial value.

In one aspect, ceramic resistive heating elements are provided that comprise three or more electrically segregated conductive zones. In another aspect, ceramic heating elements are provided that comprise a plurality of conductive zones, wherein only a portion of the conductive zones pass current during use of the heating element. In a further aspect, heating elements of the invention can be readily modified to operate at a variety of voltages. The multiple conductive zones can provide extended heating element operating lifetimes.

A wireless power receiving terminal and a wireless charging system are disclosed. A switch is arranged between any one of the input ports and any one of the output ports of a full-bridge rectifying circuit for switching the operation mode of the rectifying circuit. The full-bridge rectifying circuit operates normally when the switch is turned off. A portion of rectifying components in the full-bridge rectifying circuit operate in a half-bridge multiplying mode and the other portion of the rectifying components are short-circuited and do not operate when the switch is turned on. Thus, the rectifying mode of the rectifying circuit and then an output voltage of the rectifying circuit are adjustable, and the operation voltage range of the wireless electric energy receiving terminal is expanded and the wireless power receiving terminal can operate normally when the magnetic field intensity is relatively high or relatively low. And at the meanwhile, it is also possible to provide a post-stage circuit (such as DC-DC converter) with relatively small operation voltage range to reduce the cost.

An electric power supply system for driving an electric rotating machine has a generator supplied with driving power from an engine to generate alternating-current electric power and a matrix converter as an alternating-current to alternating-current direct converter supplied with the alternating-current electric power to output arbitrary alternating-current electric power. By driving a motor with the alternating-current electric power supplied from the matrix converter, only one time electric power conversion is carried out to provide high efficiency in the whole system. In addition, electric power loss can be reduced so as to enhance a motor output when the system is applied to a vehicle power supply system.

The invention provides a comparator and a relaxation oscillator. The comparator comprises a comparator circuit including a current mode comparator circuit; and the current mode comparator circuit consists of a first current mode comparator circuit and a second current mode comparator circuit, wherein the first current mode comparator circuit and the second current mode comparator circuit are connected with a first input terminal and a second input terminal of the comparator circuit electrically. The first current mode comparator circuit includes two N type MOS tubes and grids of the two N type MOS tubes are connected electrically; and the second current mode comparator circuit includes two P type MOS tubes and grids of the two P type MOS tubes are connected electrically. The oscillator includes the comparator. According to the invention, the production cost can be lowered; the development period can be shortened; the frequency stability is improved; and the ultra-low power consumption is realized.

The present invention provides a successive approximation register analog-to-digital converter (SAR ADC), where a high bit capacitor of the SAR ADC is composed of a plurality of sub-capacitors, and these sub-capacitors are calibrated when the SAR ADC is working. Therefore, the working speed of the SAR ADC will not be influenced. In addition, a capacitance of each sub-capacitor is lower than a redundant capacitance of the SAR ADC, therefore, input signals of the SAR ADC are allowed to have full swing.

An off chip driver circuit includes a bias circuit and a driver sub-cell circuit. The bias circuit and off chip driver sub-cell circuit are in electrical communication with each other. The bias circuit includes two serially aligned diodes which are in an off-state when the driver sub-cell is in a functional mode and which are in an on-state when the driver sub-cell is in a cold spare mode. The arrangement of the diodes enables the off chip driver circuit to handle similar voltage signals in both the functional mode and the cold spare mode.

The invention discloses a two-point modulator, a control method thereof, a DAC gain calibration method and a device. The DAC gain calibration method comprises the following steps: amplifying the gainof the second modulation circuit by N times; calculating the gain of the first modulation circuit; inputting a first baseband signal into the first modulation circuit, and inputting a second basebandsignal into the second modulation circuit; respectively acquiring the loop feedback control voltage signal and the modulation control signal, a voltage value when the DAC input data is first data, anda voltage value when the DAC input data are second data; calculating to obtain the gain of the second modulation circuit; and calibrating the gain of the DAC. By applying the method, when the gain ofthe digital-to-analog converter in the two-point modulator is calibrated, the precision requirement on the analog-to-digital converter in the two-point modulator can be reduced, so that the design difficulty is reduced.

The invention relates to the technical field of surface treatment and especially relates to a surface treatment method for improving bioactivity of a medical beta-type titanium alloy surface. The surface treatment method is characterized in that through anodic oxidation, hydro-thermal treatment and heating treatment on a titanium alloy, a composite oxide coating is formed on the surface of the titanium alloy; an inner layer is an oxide nanotube layer; the contents and element valences of Ti, Nb and Zr oxides of the inner layer change gradually; the diameter of the inner layer is in a range of 30 to 310nm; the thickness of the inner layer is in a range of 0 to 20 microns; and an outer layer is a calcium titanate layer having the thickness of 0 to 1 microns. The surface treatment method is suitable for a beta-type medical titanium alloy rich in Nb, Zr and the like. A gradient coating prepared by the surface treatment method has an integrated crystal form, has a high bone hydroxyapatite layer formation induction capacity and a high cell absorption and proliferation capacity of the surface, and has good biocompatibility. The surface treatment method can prevent the phase change and the brittle rupture caused by high temperature spaying. An oxide layer membrane is directly formed on a matrix by chemical and electrochemical principles so that the adherence between the matrix and the oxide layer membrane is improved. Through the surface treatment method, a uniform coating layer can be formed on a matrix having a complex shape without the limit of a matrix shape.

Disclosed are a design method and structure for a transistor having a relatively large threshold voltage (Vt) variation range due to exacerbated random dopant fluctuation (RDF). Exacerbated RDF and, thereby a relatively large Vt variation range, is achieved through the use of complementary doping in one or more transistor components and/or through lateral dopant non-uniformity between the channel region and any halo regions. Also disclosed are a design method and structure for a random number generator, which incorporates multiple pairs of essentially identical transistors having such a large Vt variation and which relies on Vt mismatch in pairs of those the transistors to generate a multi-bit output (e.g., a unique identifier for a chip or a secret key). By widening the Vt variation range of the transistors in the random number generator, detecting Vt mismatch between transistors becomes more likely and the resulting multi-bit output will be more stable.