EDA verification platform based on Python language and use method thereof

Abstract

The invention discloses an EDA verification platform based on a Python language and a using method thereof, relates to the FPGA logic verification technology, and provides a mode of fully utilizing Python high-level language characteristics to use a complex UVM verification environment by packaging a standard UVM verification framework. The verification platform is composed of a Python script anda UVM verification assembly. The UVM verification component is used for constructing a UVM basic verification environment. According to the invention, the Python script is used for providing the userinterface upwards; the UVM verification component is converted downwards; the Python language can be directly used for carrying out hardware verification design; according to the method, the characteristics of Python high-level language flexible data structure, object orientation, operator reloading, polymorphic multi-inheritance and the like are fully utilized, complex underlying grammars do notneed to be mastered, the work of hardware verification engineers is greatly simplified, and the quality and efficiency of hardware verification are greatly improved while the use threshold of a UVM verification environment is reduced.

Description

technical field [0001] The invention relates to the technical field of FPGA verification, in particular to an EDA verification platform based on the Python language and a method for using the same. Background technique [0002] With the continuous development of semiconductor process and integrated circuit technology, digital IC design plays an increasingly important role. In the early design, due to the small scale of the hardware and the single function, the verification engineer usually uses the teshbanch test file to verify the correctness of the logic sequence in a simulated way. Compare the actual output with the expected output to verify the correctness and completeness of the module. With the continuous improvement of FPGA resources and capacity, the hardware design has become more and more large-scale and complex, and more and more functional modules are integrated into the same IC, which is prone to complex and difficult-to-find defects, and its functions are comp...

AI Technical Summary

Problems solved by technology

[0005] Hardware verification at higher and higher levels of abstraction is the main trend of current verification methodology. Although UVM belongs to TLM-level verification and has higher efficiency than traditional RTL-level verification, it has many components and The mechanism and grammar rules also have a certain learning threshold, and the requirements for hardware verification engineers are relatively high, which is not conducive to users' rapid use and promotion

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