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Three-dimensional memory and preparation method thereof

A memory, three-dimensional technology, applied in the semiconductor field, can solve the problems of increased process and material costs, difficult contact parts, etc., to achieve the effect of reducing process and material costs, and balancing depth differences

Active Publication Date: 2020-07-28
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology

[0003] In view of this, the present application provides a three-dimensional memory and its preparation method to solve the problem of increasing the difficulty of etching all the contacts in a single step as the number of stacked layers and the stacking height continue to increase in the prior art. , easily lead to the increase of process and material cost

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  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof
  • Three-dimensional memory and preparation method thereof

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Embodiment Construction

[0041] Specific embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be practiced in other ways than those described herein, and therefore, the invention is not limited by the following embodiments.

[0042] In a three-dimensional memory such as 3D NAND flash memory, the memory array may include a core area (Core) and a stair case area (Staircase structure, SS). The step region is used to lead out contacts for the gate layer in each layer of the memory array. These gate layers are used as word lines of the memory array to perform operations such as programming, erasing, and reading.

[0043] In the manufacturing process of the three-dimensional memory, contact holes are formed by etching on the step structures of all levels in the step region, and then the contact holes are filled, so as t...

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Abstract

The invention provides a three-dimensional memory and a preparation method thereof. The preparation method comprises the steps of forming an insulating layer on the surface of a substrate; etching theinsulating layer to form a virtual stepped structure; forming a stacked structure on the surface, which deviates from the insulating layer, of the virtual stepped structure, wherein the stacked structure comprises a core region and a step region located on the periphery of the core region; etching the stacked structure in the step region to form a plurality of step structures with the same heightarranged along a first direction, wherein the first direction is a direction in which the step region points to the core region; and forming a conductive plug at one side of each step of each step structure, wherein each step of each step structure comprises a gate layer, and each conductive plug is electrically connected with the gate layer of the corresponding step. According to the invention,the problem that the process and material costs are increased easily due to the fact that the difficulty of etching all contact parts at a time becomes higher and higher along with the continuous increase of the number of stacking layers and the stacking height in the prior art is solved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a three-dimensional memory and a preparation method thereof. Background technique [0002] In the three-dimensional memory manufacturing process, in order to ensure that the contact portion can be smoothly connected to the gate in each memory array, it is necessary to form a three-dimensional (3D) ladder structure. With the rapid development of three-dimensional memory technology, the number of stacked layers of the memory array on the substrate is increasing, so the number of steps on the ladder structure is also increasing, which in turn leads to the closer to the step of the substrate, the etching forms the contact part connecting it The more difficult it is to etch, as the number of stacked layers and the stacking height continue to increase, the difficulty of etching all the contact parts at a single time will also become more and more difficult, which will easily lea...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11524H01L27/11556H01L27/1157H01L27/11582H10B41/35H10B41/27H10B43/27H10B43/35
CPCH10B41/35H10B41/27H10B43/35H10B43/27
Inventor 孙中旺赵祥辉胡军张中周文犀
Owner YANGTZE MEMORY TECH CO LTD
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