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System and method of floating point multiply operation processing

By using an integer multiplier and a floating-point multiplier in the processor to execute multiple integer multiplication and floating-point multiply-accumulate instructions, the problem of increased equipment cost and complexity in floating-point multiplication operations is solved, and efficient floating-point multiplication is achieved. Operation.

Active Publication Date: 2020-08-04
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, including a dedicated 64-bit multiplier can increase the size and cost of the processor, while converting instructions to loop operations introduces additional complexity and routing logic to the processor

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0032] Executing the second integer multiply instruction 134 causes the 32-bit integer multiplier 112 to perform integer multiplication of the low-order significant figure Sig-Lo-A 217 of the first operand and the high-order significant figure Sig-Hi-B 226 of the second operand, to generate a 53-bit value 242. The 53-bit value 242 is added to the 32-bit value 234 to generate a 55-bit value 244 (including the glue bit 235).

[0033] In one example, the second integer multiply instruction 134 is a double float multiply low-high (DFMPYLH) instruction that takes the first, 32-bit operand from RssV.uw[0] (e.g. , portion 212 storing Sig-Lo-A 217) is multiplied with the second, 21-bit operand from RttV.uw[1] (eg, Sig-Hi-B 226 from portion 221). The result of the multiplication is accumulated (added to) with the value in register RxxV.

[0034] Before performing the integer multiplication, DFMPYLH applies a mask to zero the sign bit (e.g., sign bit 224) and exponent (e.g., Exp-B 225)...

example 2

[0037] Execution of the third integer multiplication instruction 136 causes the 32-bit integer multiplier 112 to perform a high-order significant figure position Sig-Hi-A 216 of the first operand 122 and a low-order significant figure position Sig-Lo-B 227 of the second operand 124 Integer multiplication is performed to generate the 53-bit value 252. Value 252 is added to value 244 to generate 55-bit intermediate result 142 (and glue bits 235). In one example, third integer multiply instruction 136 is a DFMPYLH instruction as depicted in Example 2. Intermediate result 142 may thus include a sum of partial products (eg, values ​​232 , 242 , and 252 ), and exponents are not used in the first three operations associated with instructions 132 , 134 , and 136 .

[0038] Dedicated floating point multiply accumulate instruction 140 is executed on intermediate result 142 and at least one floating point operand to generate final floating point multiply result 144 . For example, instr...

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Abstract

A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

Description

[0001] According to 35 U.S.C. §119 Priority Claims [0002] This patent application claims priority to U.S. Nonprovisional Patent Application No. 15 / 851,390, filed December 21, 2017, by Albert Danysh et al., entitled "SYSTEMAND METHOD OF FLOATING POINT MULTIPLY OPERATION PROCESSING," which has been assigned to assignee herein, and is expressly incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates generally to processors, and more particularly to floating point multiply instruction processing. Background technique [0004] Advances in technology have led to more powerful computing devices. For example, computing devices such as laptop computers, desktop computers and servers, and wireless computing devices such as portable wireless telephones have improved computing capabilities and are capable of performing increasingly complex operations. Increased computing power also enhances device functionality in a variety of oth...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06F7/53
CPCG06F7/523G06F7/5324G06F7/485G06F7/4876
Owner QUALCOMM INC