Signal processing method, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention relates to a signal processing method, electronic equipment and a computer readable storage medium. The method implemented on the side of the device under test comprises the following steps: acquiring a plurality of signals from a plurality of logic modules operating in the same clock domain in the programmable logic device; generating a vector stream including a plurality of vectors representing the plurality of signals, respectively; adding timing information indicating a timing at which the plurality of signals are acquired to the vector stream; packaging thevector flow added with the time sequence information to generate packaged data; and sending the encapsulated data to a remote server for analysis. The method implemented at a remote server side comprises the following steps: receiving encapsulation data; determining timing information from the encapsulated data; determining a vector flow from the encapsulated data based on the timing information;and analyzing the programmable logic device by utilizing the vector flow. Therefore, a large number of on-chip signals can be conveniently monitored and acquired, the signal tracking and analysis capability is enhanced, remote analysis can be realized, the cost is greatly saved, and the convenience is improved.

Description

technical field [0001] Embodiments of the present disclosure relate to the field of signal processing, and more particularly, to a signal processing method, electronic equipment, and computer-readable storage medium used in programmable logic devices. Background technique [0002] As the density of Field Programmable Gate Array (FPGA) devices increases, it becomes impractical to connect test equipment probes to these devices under test. The capture of on-chip signals has become an effective method for locating device failures. [0003] Traditionally, a local Joint Test Group (JTAG) port is used in the field to connect the device under test to the test environment on the host computer via a dedicated converter. Both the dedicated converter and the debug tools used in the test environment will vary by FPGA vendor. In addition, the on-chip debug module mainly consists of the following parts: JTAG bridge, which is used to convert the internal parallel interface to JTAG serial ...

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Problems solved by technology

In addition, complex trigger conditions will consume considerable on-chip routing and resources, and the larger number of captured signals and longer monitoring time will also consume a lot of on-chip RAM resources

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