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Process for producing semiconductor devices and dicing lanes

A technology for semiconductors, dicing lanes, applied in the direction of semiconductor devices, semiconductor/solid state device manufacturing, processes used to create decorative surface effects, etc., to the effect of eliminating the risk of uncontrolled breakage

Pending Publication Date: 2020-08-07
SAFRAN
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0012] In contrast, for cutting heavily doped or thick semiconductors, e.g. in two active layers of doped semiconductors which are stacked and arranged above the support layer of the substrate or even in a thick single active layer The fact that it is not possible to produce dicing lines up to the edge of the substrate becomes a problem when fabricating components of the device in layers

Method used

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  • Process for producing semiconductor devices and dicing lanes
  • Process for producing semiconductor devices and dicing lanes
  • Process for producing semiconductor devices and dicing lanes

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Embodiment Construction

[0059] Combine below Figure 1 to Figure 9 A method of fabricating semiconductor device 100 in substrate 102 is described in accordance with certain embodiments. In this particular embodiment, the fabricated semiconductor device 100 is a MEMS and / or NEMS device.

[0060] like figure 1 As shown, the substrate 102 from which the semiconductor device 100 is fabricated in chip form includes a support layer 104 . The support layer 104 includes, for example, at least one semiconductor, silicon in this case, and has a thickness equal to several hundred micrometers, for example greater than or equal to about 500 μm.

[0061] The substrate 102 also includes a first dielectric or insulating layer 106 disposed on the support layer 104 . The thickness of the first dielectric layer 106 is for example between about 0.1 μm and 5 μm, in this case equal to about 2 μm, and the dielectric layer comprises for example SiO 2 .

[0062] The substrate 102 also includes a first semiconducting act...

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Abstract

Process for producing semiconductor devices (100) in a substrate (102), comprising: photolithography of a pattern of a reticle onto a portion of the substrate, defining first elements of the semiconductor devices, an exposure of the pattern being repeated a plurality of times in order to define all of the devices, photolithography of a pattern of an etch mask over all of the substrate, etching photolithography patterns into one portion of the thickness of the substrate, wherein first dicing lanes (130) encircling the devices are included in the pattern of the etch mask and / or of the reticle, and the photolithography of the etch mask defines second dicing lanes (140) defined by predetermined fracture lines of the edges of the substrate (102), and furthermore comprising the implementation ofa step of irradiating the substrate with a laser beam through the first and second dicing lanes.

Description

technical field [0001] The present invention relates to the mass production of semiconductor devices or chips, in particular for example MEMS (Micro Electro Mechanical Systems) devices and / or NEMS (Nano Electro Mechanical Systems) devices on bulk or devices such as SOI (Silicon On Insulator) or BSOI (Bond Silicon On Insulator) ) field of semiconductor-on-insulator, substrate or wafer. Background technique [0002] Substrates typically have standardized dimensions (4”, 8”, 12”, etc.) and are several hundred micrometers thick. After the steps (deposition, etching, doping, etc.) During the manufacture of semiconductor devices, one of the main steps that the substrate goes through includes dicing the substrate to separate the devices from each other to obtain individual chips. Usually, the devices obtained after this dicing have micron-scale, millimeter-scale or even External dimensions in centimeters. [0003] Various techniques exist for performing this substrate dicing. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B81C1/00H01L21/78B23K26/53
CPCB81C1/00904H01L21/78B23K26/53B23K2101/40H01L21/0275
Inventor 米卡尔·科林奥黛莉·伯舍乐
Owner SAFRAN