A bias circuit independent irrelevant to power supply voltage

Abstract

The invention discloses a bias circuit irrelevant to power supply voltage, which comprises three PMOS (P-channel Metal Oxide Semiconductor) tubes, three NMOS (N-channel Metal Oxide Semiconductor) tubes and a resistor R0, and the first PMOS tube P0 is connected into a diode structure and forms a current mirror with a second PMOS tube P1; the third NMOS tube N2 is connected into a diode structure and forms a current mirror with the first NMOS tube N0; and the source electrode of the third PMOS tube P2 is connected to the power supply VDD and forms a current branch with the third NMOS tube N2. According to the invention, the influence of the power supply voltage change on the bias current can be reduced to the greatest extent, so that the change of the system quiescent current along with thepower supply voltage can be effectively reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to a bias circuit independent of power supply voltage. Background technique [0002] With the advancement of CMOS technology, the development trend of integrated circuits is higher and higher integration, lower power supply voltage and lower power consumption; low-voltage and low-power consumption design is the mainstream direction of integrated circuit development. With the rapid development of integrated circuits, its application fields are also expanding. In some application fields such as industrial control, the power supply voltage varies widely, which requires that the design of the chip not only has low power consumption, but also can adapt to the needs of wide power supply voltage. [0003] The bias circuit provides a quiescent operating point and a bias current for other devices in the circuit to perform specific functions; to a certain extent, the magnitude of ...

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Problems solved by technology

[0006] For the above-mentioned traditional bias circuit, in the case of a relatively large power supply voltage variation range, there is a large difference in the potential of nodes A0 and B0. Due to the channel length modulation effect, the currents of PMOS transistors P0 and P1 are not equal, which will cause the output The deviation of the bias current; therefore, the current change caused by the channel length modulation effect cannot be ignored, as shown in equation (2):

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