Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method

Abstract

The invention discloses a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method, wherein the wafer-level chip structure includes: through-silicon vias, and the through-silicon vias are located from the first surface to the second surface of the wafer. The preset distance of the surface; the first surface of the wafer includes: an active area, a multi-layer redistribution line layer and bumps; the second surface of the wafer includes: an under-bump metallization layer and a concave insulating dielectric layer , the number of concave structures of the concave insulating dielectric layer is consistent with the number of the through-silicon vias, and the bottom of the concave insulating dielectric layer is cut off by the bottom of the through-silicon vias, and the under-bump metallization A layer fills the recessed insulating dielectric layer and is electrically connected to the TSV. The embodiment provided by the present application is not sensitive to the depth uniformity in the TSV blind hole etching sheet, and avoids the influence of the ultra-high selectivity ratio Si / SiOx dry etching and copper atom diffusion in the prior art on the active region.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. Background technique [0002] The key process step in the manufacture of through-silicon vias (TSVs) is the outcropping of the back of the TSV. There are two types of outcropping on the back of the TSV in the prior art: the first is to stop when the bottom of the TSV is not exposed through the thinning and polishing process, and then dry etching is used. Etch back to make TSV bumps, low-temperature SiOx / SiNx deposition, wafer polishing process, etc. realize the back exposure of TSV; the second type, firstly through the thinning and polishing process until the copper on the back of the TSV is completely exposed, and then dry etch back to make TSV bumps, low-temperature SiOx / SiNx deposition, wafer polishing, etc. to achieve TSV backside exposure. For the first so...

AI Technical Summary

Problems solved by technology

[0003] Therefore, the present invention provides a wafer-level chip structure, a multi-chip stacked interconnection structure and a preparation method, which overcome the challenges of ultra-high selectivity ratio Si / SiOx dry etching in the prior art, difficult process or diffusion of copper atoms. Drawbacks of Active Area Contamination

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