Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method

Abstract

The invention discloses a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. The wafer-level chip structure comprises a through silicon vias which are located at a preset distance from a first surface to a second surface of a wafer. The first surface of the wafer comprises an active region, a plurality of redistribution line layers and bumps; andthe second surface of the wafer comprises under-bump metallization layers and a concave insulating medium layer, wherein the number of concave structures of the concave insulating medium layer is samewith the number of the through silicon vias, the bottom of the concave insulating medium layer is separated by the bottoms of the through silicon vias, and the under-bump metallization layers fill the concave insulating medium layer and are electrically connected with the through silicon vias. The wafer-level chip structure provided by the embodiment of the invention is not sensitive to the uniformity of the depth in the TSV blind hole etching chip, and the impact on the active region from the ultrahigh selection ratio Si / SiOx dry etching and copper atom diffusion in the prior art is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. Background technique [0002] The key process step in the manufacture of through-silicon vias (TSVs) is the outcropping of the back of the TSV. There are two types of outcropping on the back of the TSV in the prior art: the first is to stop when the bottom of the TSV is not exposed through the thinning and polishing process, and then dry etching is used. Etch back to make TSV bumps, low-temperature SiOx / SiNx deposition, wafer polishing process, etc. realize the back exposure of TSV; the second type, firstly through the thinning and polishing process until the copper on the back of the TSV is completely exposed, and then dry etch back to make TSV bumps, low-temperature SiOx / SiNx deposition, wafer polishing, etc. to achieve TSV backside exposure. For the first so...

AI Technical Summary

Problems solved by technology

[0003] Therefore, the present invention provides a wafer-level chip structure, a multi-chip stacked interconnection structure and a preparation method, which overcome the challenges of ultra-high selectivity ratio Si / SiOx dry etching in the prior art, difficult process or diffusion of copper atoms. Drawbacks of Active Area Contamination

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