Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method

Abstract

The invention discloses a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. The wafer-level chip structure comprises through silicon vias penetrating through a wafer; a first surface of the wafer comprises an active region, a plurality of redistribution line layers and bumps; and a second surface of the wafer comprises an insulating dielectric layer and frustum transition structures connected with the through silicon vias. According to the embodiment of the invention, the frustum-shaped impedance transition structures are introduced between TSV exposed areas on the back surface of the wafer and the UBM to make impedance matching between the TSV and the UBM realized, so that the problem of signal distortion caused by sudden change of impedance is solved; and compared with a traditional scheme, in order to achieve the frustum-shaped transition structures of the scheme, the number of photomasks is not increased, only one photoetching process and one reactive ion etching process are added on the basis of the original process, so that the process flow is not complex.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. Background technique [0002] In recent years, in the application of 3D stacking of multi-layer chips using TSV (Through Silicon Via) and micro-bumps, the electrical signal transmission path between the upper and lower stacked chip layers is: the RDL of the upper chip layer, the upper chip layer Buried vertical interconnection (TSV), bonding micro-bumps between the upper and lower chip layers, UBM of the lower layer chip, embedded vertical interconnection (TSV) of the lower layer chip and RDL of the lower chip layer. On the signal transmission path, the impedance of the transmission line is constantly changing, and the change and fluctuation of the impedance will have a significant impact on the quality of the signal transmission, such as the reduction of the ey...

AI Technical Summary

Problems solved by technology

[0004] Therefore, the present invention provides a wafer-level chip structure, a multi-chip stacked interconnection structure and a preparation method, which overcome the problem in the prior art that the impedance of the signal transmission path is constantly changing during 3D chip packaging or wafer-level packaging. Defects that cause a noticeable impact on signal transmission quality

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