Wafer-level chip structure, multi-chip stacking interconnection structure and preparation method

Abstract

The invention discloses a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method, wherein the wafer-level chip structure includes: a through-silicon hole penetrating the wafer, and its first surface includes: an active area, a multi-chip The second surface of the layer redistribution line layer and the bump includes: an insulating dielectric layer, and a cone-truncated transition structure connected with the through-silicon hole. In the embodiment of the present invention, a frustum-type impedance transition structure is introduced between the TSV outcrop area on the back of the wafer and the UBM, so that the impedance matching between the TSV and the UBM is realized, and the signal distortion problem caused by the impedance mutation is improved. Compared with the traditional solution, In order to realize the frustum-shaped transition structure of this solution, the number of masks is not increased, but only one-step photolithography process and one-step reactive ion etching process are added on the basis of the original process, and the process flow is not complicated.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a wafer-level chip structure, a multi-chip stacking interconnection structure and a preparation method. Background technique [0002] In recent years, in the application of 3D stacking of multi-layer chips using TSV (Through Silicon Via) and micro-bumps, the electrical signal transmission path between the upper and lower stacked chip layers is: the RDL of the upper chip layer, the upper chip layer Buried vertical interconnection (TSV), bonding micro-bumps between the upper and lower chip layers, UBM of the lower layer chip, embedded vertical interconnection (TSV) of the lower layer chip and RDL of the lower chip layer. On the signal transmission path, the impedance of the transmission line is constantly changing, and the change and fluctuation of the impedance will have a significant impact on the quality of the signal transmission, such as the reduction of the ey...

AI Technical Summary

Problems solved by technology

[0004] Therefore, the present invention provides a wafer-level chip structure, a multi-chip stacked interconnection structure and a preparation method, which overcome the problem in the prior art that the impedance of the signal transmission path is constantly changing during 3D chip packaging or wafer-level packaging. Defects that cause a noticeable impact on signal transmission quality

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