An overlay alignment mark structure and related method and device
A technology for aligning marks and markings, which is applied in the direction of electric solid devices, semiconductor devices, semiconductor/solid device components, etc., can solve the problem of large measurement errors of overlay accuracy and achieve the effect of small measurement errors
Active Publication Date: 2021-11-05
YANGTZE MEMORY TECH CO LTD
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During the manufacturing process of existing semiconductor devices, the measurement error of overlay accuracy is relatively large
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[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.
[0038] As mentioned in the background art, with the continuous reduction of the feature size of lithography, the requirements for the overlay accuracy and critical dimension uniformity of the lithography machine are also continuously increased. The manufacture of semiconductor devices usually includes dozens of photolithography processes. In order to ensure the corresponding relationship of each level, it is necessary to require an overlay accuracy that matches...
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The invention provides an overlay alignment mark structure and its manufacturing method, an overlay accuracy measurement method and a semiconductor device, including a substrate; a physical reference mark located on one side of the substrate; and a film covering the side of the physical reference mark away from the substrate layer, the side of the film covering layer facing away from the substrate includes a groove measurement mark, and the combination of the physical reference mark and the groove measurement mark is an overlay alignment mark; there is at least one overlapping area between the groove measurement mark and the physical reference mark, and in The overlapping region exposes at least one side of the physical reference mark. Since there is at least one overlapping area between the groove measurement mark and the physical reference mark, and at least one side of the physical reference mark is exposed in the overlapping area, a clearer and more accurate physical reference mark and the groove can be obtained by the CDSEM measuring machine. The groove measures the shape of the mark at the overlapping area, and then measures the overlay accuracy of the clear and precise shape, which can ensure that the measurement error of the overlay accuracy is small.
Description
technical field [0001] The invention relates to the technical field of semiconductor devices, and more specifically relates to an overlay alignment mark structure and a manufacturing method thereof, a method for measuring overlay accuracy and a semiconductor device. Background technique [0002] With the continuous reduction of lithographic feature size, the requirements for overlay accuracy and critical dimension uniformity of lithography machines are also increasing. The manufacture of semiconductor devices usually includes dozens of photolithography processes. In order to ensure the corresponding relationship of each level, it is necessary to require an overlay accuracy that matches the photolithography feature size. The difference between the exposure pattern and the actual position, that is, the pattern position offset, is an important factor affecting the overlay accuracy of the lithography machine, and is also an important factor affecting the device. In the manufact...
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IPC IPC(8): G03F7/20H01L23/544
CPCG03F7/70633H01L23/544H01L2223/54426Y02P70/50
Inventor 方超高志虎
Owner YANGTZE MEMORY TECH CO LTD