A reconfigurable three-dimensional microsystem packaging structure and packaging method
A packaging structure and three-dimensional packaging technology, which is applied in the fields of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems that sub-modules cannot be independently tested, and three-dimensional micro-systems of subsystem modules cannot be used, so as to expand the applicable field. , the effect of increasing the degree of freedom
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0042] see figure 1 , in one embodiment, a reconfigurable three-dimensional microsystem packaging structure, including: at least two two-dimensional subsystem modules, a three-dimensional packaging layer, the two-dimensional subsystem modules are stacked in sequence and communicate with each other in electrical signals; the three-dimensional packaging layer is arranged on The stacked two-dimensional subsystem modules are used to package the stacked two-dimensional subsystem modules, and the outer surface of the three-dimensional packaging layer is provided with a surface metallization conductor wiring layer 113;
[0043] The two-dimensional subsystem module includes a chip carrier, an adapter board 104, at least two chips 106, a test interconnection structure corresponding to the chips 106, and a two-dimensional packaging layer; the adapter board 104 is arranged on the chip carrier; the chips 106 are all Set on the adapter plate 104, and form an electrical signal connection th...
Embodiment 2
[0058] This embodiment is a packaging method for a reconfigurable three-dimensional microsystem packaging structure, which is used to produce the reconfigurable three-dimensional microsystem packaging structure in the first embodiment above, and the steps are as follows:
[0059] S1: Provide a chip carrier, open at least two required first through holes on the chip carrier, and set in-plane vertical interconnection 105 in the first through holes; use thin film deposition equipment and pattern electroplating on the surface of the chip carrier The equipment performs metallization layer 117 preparation;
[0060] S2: Provide an adapter board 104, the surface of the adapter board 104 is prepared with thin film deposition equipment and pattern electroplating equipment to prepare the metallization layer and respectively form a corresponding subsystem functional circuit unit with the chip 106; and on the adapter board 104, Mounting the chip 106 using a low temperature soldering proces...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


