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Electrical circuit for testing primary internal signals on an asic

A technology of internal signals and circuits, used in the measurement of electricity, measurement of electrical variables, digital circuit testing, etc.

Active Publication Date: 2020-09-01
ROBERT BOSCH GMBH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] If, for example, the internal mains voltage here has to be small enough for testing purposes that the voltage supply derived from the internal mains supply is not sufficient for operating the digital part, then in some cases it may not be possible to examine the internal mains voltage via the test interface. Reset signal supplied by main voltage or power-on-reset signal (Power-on-Reset-Signal)

Method used

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  • Electrical circuit for testing primary internal signals on an asic
  • Electrical circuit for testing primary internal signals on an asic
  • Electrical circuit for testing primary internal signals on an asic

Examples

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Embodiment Construction

[0040] Within the scope of the description of an embodiment of the invention, the voltage at a connection or network relative to ground potential GND is for example U for connection TEST TEST Indicates that for network VDD use U VDD express. The current flowing into the connector, for example, for the ASIC connector TEST, uses I TEST express.

[0041] figure 1 An exemplary embodiment of a circuit for testing digital signals is shown in , which is only suitable for testing internal digital signals according to the first circuit technology implementation. Schmitt Trigger SMT applied at greater than 1 When the voltage of the switching threshold is reached, the ASIC connector TEST can be switched to the test mode. This is shown by a high level at the output terminal connector TM of the switching circuit, which is connected to the Schmitt trigger SMT 1 output connection. Schmitt trigger SMT 1 and AND gate X 1 to X n Depend on figure 1 Not shown in the supply voltage U V...

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PUM

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Abstract

The invention relates to an electrical circuit for testing primary internal signals on an ASIC, wherein just one test pin (TEST) is provided via which it is possible to select a digital or analogue signal to be monitored (D1, D2-Dn; A1, A2-An). The electrical circuit comprises a Schmitt trigger (SMT1) arranged between the test pin (TEST) and an output connection (TM) of the electrical circuit, wherein a test mode is activated when a switching threshold of the Schmitt trigger (SMT1) is exceeded and at least one partial circuit is provided for monitoring a digital signal (D1, D2-Dn) having a resistor (R1, R2-Rn), an NMOS transistor (M1, M2- Mn) and an AND gate (X1, X2-Xn), to the first input of which the digital signal (D1, D2-Dn) is applied, wherein the resistor (R1, R2-Rn) is arranged between the test pin (TEST) and the drain connection of the NMOS transistor (M1, M2-Mn), the source connection of the NMOS transistor (M1, M2-Mn) is connected to earth, the gate connection of the NMOS transistor (M1, M2-Mn) is connected to the output of the AND gate (X1, X2-Xn) and the second input of the AND gate (X1, X2,..., Xn) is connected to the output connection (TM) of the electrical circuit.

Description

technical field [0001] The invention relates to a circuit for testing the main internal signals of an ASIC, wherein only one test pin (Test-Pin) is provided, through which the selection of one or more digital signals to be investigated or the selection of analog Signal. Background technique [0002] Application-specific integrated circuits (ASICs) are tested during their manufacture and before they are delivered. To do this, it must be possible to provide internal digital and / or analog signals that can be investigated or measured via the test interface. For this purpose, the ASIC is usually placed in a test mode in which digital and / or analog signals can be switched via a multiplexer to one or more individual connections of the ASIC. The signals to be tested in succession can generally be selected, for example via a serial peripheral interface (SPI) or by means of an interface according to IEEE standard 1149.1 (also called Joint Test Action Group, JTAG, Joint Test Action G...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3167G01R31/317
CPCG01R31/3167G01R31/31701G01R31/31703G01R31/3172
Inventor C·赫尔曼
Owner ROBERT BOSCH GMBH