Low-delay thin film transistor, array substrate and display panel

Abstract

The invention provides a low-delay thin film transistor, an array substrate and a display panel. The low- delay thin film transistor comprises a grid electrode, an active layer arranged at one side ofthe grid electrode, and a source electrode and a drain electrode arranged over the grid electrode; the source electrode and the drain electrode are connected with the active layer; and in the direction perpendicular to the active layer, at least part of the orthographic projection of the drain electrode is located outside the orthographic projection of the grid electrode. At least part of the drain electrode extends out of an area where a grid electrode is located, so that at least part of the orthographic projection of the drain electrode is located outside the orthographic projection of thegrid electrode in the direction perpendicular to the active layer; and thus, the opposite overlapping area of the drain electrode and the grid electrode is reduced, the coupling capacitance of the drain electrode and the grid electrode is reduced, the resistance-capacitance delay is reduced, and the display performance of the display panel is improved.

Description

technical field [0001] The present application relates to the display field, in particular to a low-latency thin film transistor, an array substrate and a display panel. Background technique [0002] With the development of display technology, in high refresh rate and high resolution liquid crystal display panels such as 120Hz frequency and 8K pixels, signal delay is a key factor restricting the further development of liquid crystal display panels. In TFT (Thin Film Transistor; Thin Film Transistor) Among them, the capacitance value between the gate and the source-drain is directly affected by its overlapping area. At present, in the structure of thin film transistors, the drain is placed on the gate metal as a whole, and the overlapping area between the drain and the gate is relatively small. Large, resulting in a large drain-to-gate coupling capacitance, making the overall resistance-capacitance delay of the display panel relatively large, which affects the display perform...

AI Technical Summary

Problems solved by technology

[0004] The present application provides a low-latency thin film transistor, an array substrate and a display panel to solve the problem that in the structure of the existing thin film transistor, the overlapping area between the drain and the gate is large, resulting in a large coupling capacitance between the drain and the gate, which makes the The overall resistance and capacitance delay of the display panel is relatively large, which affects the technical problem of the display performance of the display panel

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