Data splicing instruction processing method and data splicing instruction processing device

Abstract

An instruction processing device includes a first vector register adapted to store a first vector to be operated, a second vector register adapted to store a second vector to be operated, a decoder adapted to receive and decode a data splicing instruction, and an execution unit. The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, the splicing identifier, and the destination. The execution unit is coupled to the first vector register, the second vector register and the decoder, is suitable for executing the decoded data splicing instruction, so as to acquire a first part of the first vector from the first vector register according to the splicing identifier, acquire a second part of the second vector from thesecond vector register according to the splicing identifier, splice the acquired first part of the first vector and the acquired second part of the second vector to form a third vector, and stores thethird vector into the destination.

Description

technical field [0001] The invention relates to the field of processors, in particular to a processor core and a processor with an instruction set of data splicing instructions. Background technique [0002] As processor technology has evolved, SIMD instructions have emerged. SIMD refers to instructions with a Single Instruction Multiple Data structure. Usually, a single instruction performs processing such as addition, subtraction, multiplication, and division on a single data, while SIMD instructions can perform the same operation on multiple sets of data in parallel. The SIMD instruction is suitable for the quantity of vector data because of its characteristics. For example, it is widely used in the VDSP instruction of the vector digital signal processing instruction set, and the VDSP instruction set is suitable for data processing under special complex tasks, such as Audio signals, image signals and artificial intelligence, etc., are therefore an integral part of the m...

AI Technical Summary

Problems solved by technology

This also causes the vector data not to be aligned according to the address, so when the data at the address is loaded into the vector register through the VDSP read instruction, the arrangement of the elements of the vector data is not aligned

[0004] On the other hand, even if each element of the vector data can be aligned on the memory address, since the total size of the vector data is not a multiple of the bit width of the vector register, when the user loads the vector data into the vector register, it will inevitably be The last data loaded into the vector register cannot completely fill the entire register, resulting in some invalid information remaining in the vector register

Invalid information may be misused if used incorrectly

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