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Radiation-hardened d flip-flop circuit

A flip-flop and circuit technology, applied in logic circuits, radiation resistance enhancement, electrical components, etc., can solve problems such as large circuits and spaces, single-event interference, and multiple power

Pending Publication Date: 2020-10-23
BAE SYST INFORMATION & ELECTRONICS SYST INTERGRATION INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Many integrated circuit devices with digital logic circuits are susceptible to single-event disturbances due to radiation, and conventional flip-flop circuits and latches are no exception
Additional measures can be added to conventional flip-flop circuits and latches to make them more impervious to single-event disturbances, but significant additional circuitry and space is required to provide separation of sensitive nodes
However, a large amount of additional circuitry is not desirable for implementation on aircraft and / or spacecraft, and definitely not acceptable on small technology nodes, as it would result in circuits that consume more power while taking up more silicon area

Method used

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  • Radiation-hardened d flip-flop circuit
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  • Radiation-hardened d flip-flop circuit

Examples

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Embodiment Construction

[0017] Referring now to the attached drawings, in particular to the figure 1 , shows a schematic diagram of a D flip-flop (DFF) circuit according to the prior art. As shown, the DFF circuit 10 includes a master latch 11 and a slave latch 12 . Master latch 11 includes first and second clocked inverter stages 14-15 and a first (unclocked) inverter INV1. The first clock inverter stage 14 comprises a p-channel clock switch SP1 , a p-channel data device MP1 , an n-channel data device MN1 , and an n-channel clock switch SN1 all connected in series. The second clock inverter stage 15 comprises a p-channel clock switch SP2, a p-channel data device MP2, an n-channel data device MN2, and an n-channel clock switch SN2 all connected in series. Similarly, slave latch 12 includes third and fourth clock inverter stages 16-17, clock switches SP3, SN3, SP4, and SN4 of similar configuration, and data devices MP3, MN3, MP4, and MN4, and a second (non-clocked) inverter INV2.

[0018] The in-p...

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PUM

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Abstract

A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual -input inverter, a single-input tri-state inverter, a dual -input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.

Description

technical field [0001] The present disclosure relates generally to electronic circuits, and more particularly to flip-flop circuits. More specifically, the present disclosure relates to a radiation hardened D flip-flop circuit. Background technique [0002] Digital logic systems typically include combinational and sequential circuits. Combinational circuits are made up of logic gates whose output is determined by a current input. Combinational circuits perform operations logically represented by Boolean expressions. [0003] Sequential circuits include logic gates and storage elements called flip-flops and latches. The output of the storage element is a function of the current input and the state of the storage element based on previous input. Therefore, the output of a sequential circuit is the result of the current input and the previous input, and the operation of the sequential circuit is determined by the internal state and the timing of the input. [0004] Many in...

Claims

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Application Information

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IPC IPC(8): H03K19/003H03K3/356
CPCH03K3/356069H03K3/35625H03K19/00338H03K19/0033
Inventor B·李D·波斯特多L·J·凯里N·奇奥里诺P·弗莱明D·D·莫瑟尔
Owner BAE SYST INFORMATION & ELECTRONICS SYST INTERGRATION INC
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