Floating gate type FLASH synaptic device structure and preparation method thereof
A technology of synapse device and floating gate type, which is applied in the field of floating gate FLASH synapse device structure and its preparation, and can solve the problems of low integration and complex structure
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Embodiment 1
[0037] The present invention provides a floating gate type FLASH synaptic device structure, including a plurality of floating gate type FLASH synaptic device units, and its structural principle is as follows figure 1 shown. The device of this structure is a 7-terminal device, including source S1, drain D1, substrate B1 of the first floating gate MOS transistor, source S2, drain D2, substrate B2 and control gate CG of the second floating gate MOS transistor; and The first floating gate MOS transistor and the second floating gate MOS transistor share the control gate CG and the common floating gate FG, and control the electrons on the floating gate through programming and erasing, so as to realize the multiplication of the first floating gate MOS transistor and the second floating gate MOS transistor A state of storing information. Specifically, the floating gate type FLASH synaptic device unit of the present invention is composed of two FLASH devices, which are respectively on...
Embodiment 2
[0047] The invention provides a method for preparing a floating gate type FLASH synaptic device structure, comprising:
[0048] A silicon base is provided as a substrate 00, on which the required deep N well 01, high voltage P well 02, STI isolation trench 03, T1 active region 11 and T2 active region 22 are fabricated sequentially; the STI The depth of isolation groove 03 is The isolation between the active regions of T1 and T2 is realized through the STI isolation groove 03;
[0049] According to the industry standard CMOS process, a sacrificial oxide layer is fabricated on the substrate 00, and trench modulation photolithography and implantation are performed on the T1 active region 11 and the T2 active region 22 to realize different intrinsic threshold voltages of T1 and T2;
[0050] Using the above surface as the substrate, remove the sacrificial oxide layer by wet method, and grow a layer of tunnel oxide layer 04; cover the above surface with N-type polysilicon layer 05...
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