MTP memory cell

Abstract

The invention discloses an MTP memory cell. The MTP memory cell comprises a select transistor N1, a programmable capacitor C1 and an erasable capacitor C2. The drain gate of the select transistor N1 is adopted as the bit line BL of the MTP memory cell. The source gate of the select transistor N1 is adopted as the source gate SG of the whole MTP memory cell. The upper polar plate of the programmable capacitor C1 and the grid electrode of the select transistor N1 are connected and share a common floating poly. The lower polar plate of the programmable capacitor C1 is adopted as the word line WL of the whole MTP memory cell. The upper polar plate of the erasable capacitor C2 is adopted as the erase gate EG of the MTP. The lower polar plate of the erasable capacitor C2 and the upper polar plate of the erasable capacitor C1 are connected and share a common floating gate. According to the MTP memory cell provided by the invention, improvement and optimization are made to a traditional MTP memory cell, common logic processes can be embed and extra masks and technology are not needed. The MTP memory cell provided by the invention has a wider application scope and has high programming efficiency on various digital and digital-analog hybrid technology platforms. Compared with an MTP memory cell at present, the MTP memory cell provided by the invention has higher programming efficiency and better erase performances and reliability, and can decrease the area of the MTP memory cell.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an MTP storage unit. Background technique [0002] Using Floating poly (floating gate) to store electrons is a common MTP (Multi-time programmable) device (such as figure 1 , figure 2 As shown), it can be embedded in a common logic process without adding additional masks and processes, such as US Patent US7515478B2. The MTP of this structure is composed of three PMOS devices, using PMOS hot electron injection (CHE) for programming, and FN tunneling mechanism for data erasure of memory cells. The MTP memory cell with this structure is the most commonly used device architecture in the semiconductor industry at present. [0003] The programming process is accomplished through the hot electron effect (CHE). When the gate oxide film of the programming transistor T2 is thicker, the energy required for the channel current to decrease and the hot electrons to penetrate the ...

AI Technical Summary

Problems solved by technology

The reason is that under high voltage, if the N well spacing is not sufficient, it is easy to cause punch through (punch through), and the N well spacing directly affects the area of ​​the MTP memory cell

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