An FPGA-based configurable ro PUF

Abstract

The present invention proposes an FPGA-based configurable RO PUF, including at least two ring oscillators, two counters and a comparator implemented based on FPGA. The ring oscillator includes an AND gate and n+1-order configurable delay units. By configuring these delay units with excitation signals, the RO PUF can be configured into different structures, so that the RO PUF proposed by the present invention has more oscillation situations , resulting in more stimulus-response pairs. On the other hand, it also makes the mathematical delay model of ROPUF more complicated, which increases the difficulty of machine learning modeling and improves the resistance of CRO PUF to machine learning algorithm attacks.

Description

technical field [0001] The invention relates to the field of physically unclonable functions of reconfigurable ring oscillators, in particular to an FPGA-based configurable RO PUF. Background technique [0002] Information security of computing systems, from server clusters to nodes, is critical for the Internet of Things (IoT). Traditional security primitives such as the Advanced Encryption Standard (AES) are impractical for resource-constrained or battery-based devices. The method of storing keys in non-volatile memory (NVM) is also vulnerable to intrusive attacks. Physically Unclonable Functions (PUFs) are considered as promising hardware security primitives due to their energy efficiency and economy. [0003] Because ring oscillator (RO) PUFs are field-programmable gate array (FPGA) friendly and can be easily deployed on FPGA-based platforms, it has gradually become one of the most popular PUF designs. Each RO in the RO PUF consists of a fixed delay device to form a s...

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Problems solved by technology

Moreover, the implementation of traditional different CRO PUF structures needs to be redeployed on the FPGA development board, which also leads to higher hardware costs

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