Efficient multi-mode verification platform and method

A verification platform and verification method technology, applied in the field of efficient multi-mode verification platform, can solve the problems of low verification efficiency, poor quality, and difficult maintenance of verification platform, and achieve the effect of avoiding management difficulties and reducing cumbersome operations.

Pending Publication Date: 2020-11-17
HUNAN ADVANCECHIP ELECTRONICS TECH CO LTD
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Problems solved by technology

[0005] The invention provides an efficient multi-mode verification platform and method, and its purpose is to solve the problems of low verification efficiency, poor quality and difficult maintenance of the verification platform of the traditional verification platform

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  • Efficient multi-mode verification platform and method
  • Efficient multi-mode verification platform and method
  • Efficient multi-mode verification platform and method

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Embodiment Construction

[0074] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

[0075] The invention provides an efficient multi-mode verification platform and method aiming at the problems of low verification efficiency, poor quality and difficult maintenance of the verification platform in the existing verification platform.

[0076] Such as figure 1 As shown, the embodiment of the present invention provides a kind of efficient multi-mode verification platform, comprising: asic module, described asic module comprises the software emulation platform of chip design and configuration file; config module, described config module comprises multi-mode verification A global configuration file of the platform; an fpga module, the fpga module includes an FPGA system prototype verification platform and a configuration file.

[0077] Such a...

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Abstract

The invention provides an efficient multi-mode verification platform and method, and the method comprises the steps: 1, inputting a test excitation into the multi-mode verification platform, enablingthe multi-mode verification platform to call a library and an IP, and carrying out the software simulation verification; 2, finding an error in the software simulation verification process, returningthe error to the DUT directory, and modifying a chip design file; and 3, executing FPGA hardware system prototype verification when no error occurs in the software simulation verification process. According to the method, software simulation verification and FPGA hardware system prototype verification under the FPGA development condition are compatible, software simulation verification supports parallel simulation of a single testcase or multiple testcases, each testcase simulation result has respective space storage and cannot be covered, a multi-mode verification platform supports automaticreading and real-time refreshing of design files. Automatic full compilation and manual step-by-step compilation can be supported, engineering file management difficulty is effectively avoided, and tedious operation of engineering compilation and online debugging is reduced.

Description

technical field [0001] The invention relates to the technical field of digital integrated circuit design and verification, in particular to an efficient multi-mode verification platform and method. Background technique [0002] The famous Moore's Law states that the number of transistors that can be accommodated in an integrated circuit chip will double every about 18 months, and the performance will also double, which makes the chip more and more complex, giving digital integrated circuits The verification work has brought severe challenges. The current verification can be divided into two modes, one is software simulation verification, and the other is hardware system prototype verification. [0003] Software simulation verification is based on verification methodology (UVM, VMM, etc.) through language programming to establish test incentives for verification. This verification method has a complex environment, heavy programming, simulation, and debugging work, and it is d...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/33
CPCG06F30/33
Inventor 谭振平易峰吕华智陈毅华王超
Owner HUNAN ADVANCECHIP ELECTRONICS TECH CO LTD
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