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Circuit structure and update method of fast routing update based on hardware implementation

A technology for hardware implementation and circuit update, applied in electrical components, electrical digital data processing, memory address/allocation/relocation, etc., can solve the problems of occupying clock cycles, routing updates to CPU load, complex trie tree structure, etc. The effect of reducing occupancy, reducing logic complexity, and improving memory utilization

Active Publication Date: 2022-07-08
ARMY ENG UNIV OF PLA
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although solutions based on dedicated hardware can achieve a throughput rate of hundreds of G, these solutions require the CPU to assist in maintaining a trie-based data structure for updating and expanding all routing prefixes into forwarding data structures stored in hardware. However, trie The tree structure is complex. Inserting and deleting operations in the trie tree takes a lot of clock cycles. As the frequency of routing updates continues to increase, routing updates cause a large load on the CPU.

Method used

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  • Circuit structure and update method of fast routing update based on hardware implementation
  • Circuit structure and update method of fast routing update based on hardware implementation
  • Circuit structure and update method of fast routing update based on hardware implementation

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Embodiment Construction

[0026] The present invention will be further described below in conjunction with the accompanying drawings.

[0027] like figure 1 As shown, the present invention is based on a hardware-based fast routing update circuit structure, including a linked list management module, a head pointer management module, a shared storage area management module, and a structure conversion module;

[0028] The linked list management module is used to manage the trie tree converted into a linked list structure, record the specific structure of the sub-trie in the trie, perform node insertion and deletion operations on the trie, and write the prefix involved in the operation and the information carried by the prefix after the update is completed. prefix_FIFO;

[0029] The head pointer management module is used for managing the linked list head pointers in the linked list structure, and performs search, addition and deletion operations issued by the linked list management module;

[0030] The s...

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PUM

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Abstract

The invention discloses a hardware-based fast routing update circuit structure and an implementation method. A linked list management module in the circuit is used to record the specific structure of the sub-trie obtained by layering the trie, and can add and delete nodes to the trie. operation, after the update is completed, the prefix involved in the operation is sent to the structure conversion module; the head pointer management module manages the head pointer of the linked list, which is used to perform the add and delete operations issued by the linked list management module; the shared storage area management module is used to manage the shared RAM. The empty address can be used to perform read and write operations issued by the linked list management module; the structure conversion module is used to convert the linked list into a forwarding table used by the search device. The circuit can replace the processor to realize routing update and maintenance functions, and can realize fast addition and fast deletion of routing table entries.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a hardware-based fast routing update circuit structure. Background technique [0002] At present, the route lookup algorithm scheme is mainly divided into two types, one is a software-based scheme and the other is a hardware-based scheme. Software-based solutions usually do not depend on specific hardware, so they are more flexible and easy to port to different platforms. Most software-based approaches focus on reducing memory requirements and reducing the number of memory accesses. Hardware-based solutions utilize dedicated hardware (including TCAMs, network processors, FPGAs, and GPUs) to achieve better performance. [0003] In order to take advantage of the high-speed parallelism of dedicated hardware, hardware-based solutions often limit the number of prefix lengths by using controllable prefix extension technology to form a forwarding data structure that suppor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04L45/02H04L45/745G06F12/02
CPCH04L45/02H04L45/54H04L45/745G06F12/023
Inventor 王乾乔庐峰陈庆华
Owner ARMY ENG UNIV OF PLA
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