Configurable multi-input multi-output FIFO design method and device

Abstract

The invention discloses a multi-input and multi-output FIFO (First In First Out), which comprises a control unit fifotl and a data storage unit fifodp, and is characterized in that three groups of signals including a signal wren, a read pointer rptr and a write pointer wptr are connected between the output end of the control unit fifotl and the data storage unit fifodp. The invention is suitable for various scenes; the invention further provides a configurable design method for the multi-input and multi-output FIFO, the configurable design work of the multi-input and multi-output FIFO can be achieved, various FIFO queues can be achieved by compiling python codes at a time, the design process can be greatly accelerated, and design defects are reduced.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a design method and device for a configurable multi-input multi-output FIFO, including a multi-input multi-output FIFO and a configurable design method for the multi-input multi-output FIFO. Background technique [0002] In chip design, in order to realize the temporary storage requirements of data in signal processing, queues of various widths and lengths are usually set. Generally speaking, in view of the pipelined data flow mode in digital chip design, the queues used therein are First-In-First-Out (FIFO) queues. Moreover, FIFOs with various input widths, storage widths, output widths, and flow control strategies will be used simultaneously in the same design. Although the basic functions of these queues are the same, their input width, storage width, output width and flow control strategy are different, so that these queues are usually designed separately: according to the require...

AI Technical Summary

Problems solved by technology

This makes the method unable to support more input and output width combinations, and the codes between different combinations are basically parallel, and still need to be designed and verified separately

[0004] It can be seen that none of the existing methods can truly realize the configurability of multi-input and multi-output FIFOs, which greatly increases the cost of chip design and increases the difficulty of performance exploration based on configurability.

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