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Method and system for memory coupling compilation of reconfigurable chips

A compiling method and compiling system technology, applied in the field of reconfigurable processor development, can solve the problems of vague use and incorrect use, etc.

Active Publication Date: 2021-07-02
BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Among them, mapping and memory access are important factors of the compiler. The existing compilation schemes are vague about the use of the two, which has caused the situation that they cannot be used correctly.

Method used

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  • Method and system for memory coupling compilation of reconfigurable chips
  • Method and system for memory coupling compilation of reconfigurable chips
  • Method and system for memory coupling compilation of reconfigurable chips

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Embodiment Construction

[0040] In order to have a clearer understanding of the technical features, purposes and effects of the invention, the specific embodiments of the present invention are now described with reference to the accompanying drawings, in which the same reference numerals represent components with the same or similar structures but the same functions.

[0041] In this article, "schematic" means "serving as an example, example or illustration", and any illustration or implementation described as "schematic" should not be interpreted as a more preferred or more advantageous Technical solutions. In order to keep the drawings concise, the drawings only schematically show the parts related to this exemplary embodiment, and they do not represent the actual structure and true proportion of the product.

[0042] One aspect of the present invention provides a memory coupling compiling method for a reconfigurable chip, such as figure 1 As shown, the memory-coupled compilation method for reconfi...

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Abstract

The present invention provides a memory coupling compiling method and system for a reconfigurable chip, comprising: obtaining the cycle number of the DFG data flow graph; obtaining the linear transformation vector of the cycle number through the mapping time difference; judging whether the heuristic algorithm can be used to obtain the cycle number The linear array of the linear transformation vector is obtained according to the judgment result or the memory mapping result obtained through the current DFG data flow graph, and the current DFG data flow graph is adjusted until the linear array is obtained. The present invention adjusts each node in the DFG data flow diagram to meet the requirement of obtaining a linear array, greatly reduces the compilation time, and the user has a strong compiling experience. High practicability, not only reconfigurable acceleration chips are available, but also high reusability for programmable devices.

Description

technical field [0001] The invention relates to the development of a reconfigurable processor, and is applied to a compiler and compiling process of a reconfigurable compiler. The invention specifically relates to a memory coupling compiling method and system for a reconfigurable chip. Background technique [0002] In the compilation process of the compiler for the typical reconfigurable processor CGRA based on the LLVM compilation framework (Low Level Virtual Machine) compilation framework, its main goal is to make the user's application common through the front end of the LLVM compilation framework of the reconfigurable compiler After the lexical, grammatical and semantic analysis, the intermediate expression (IR, Intermediate Representation) is optimized and the appropriate data flow graph is extracted. After task division and storage allocation, operator scheduling and mapping work, etc., the application needs to be generated in The binary configuration information (Con...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/41G06F9/54G06F15/78
CPCG06F8/41G06F9/544G06F15/7867
Inventor 胡俊宝张振欧阳鹏
Owner BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
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