Core partition circuit and test device

Abstract

A core partition circuit comprises a first decompression circuit, a second decompression circuit, a first switching circuit, an isolation scanning circuit, a first compression circuit and a second switching circuit. The first decompression circuit receives and decompresses an input signal. The second decompression circuit receives and decompresses the input signal. The first switching circuit outputs an output signal of the first decompression circuit or the second decompression circuit according to the first control signal. The isolation scanning circuit is coupled to the first switching circuit and receives the output signal of the first decompression circuit or the second decompression circuit so as to scan the interior or the port of the core partition circuit. The first compression circuit is coupled to the isolation scanning circuit and receives and compresses internal logic of the core partition circuit. The second compression circuit is coupled to the isolation scan circuit toreceive and compress the port logic of the core partition circuit. The second switching circuit is coupled to the first compression circuit and the second compression circuit, and outputs internal logic or port logic of the compressed core partition circuit according to the first control signal.

Description

technical field [0001] The invention relates to the field of system chips, in particular to a core partition circuit and a testing device. Background technique [0002] In the design of a traditional design for testability (DFT) device (hereinafter referred to as a test device), the isolation chain (wrapper chain) of each core partition (core partition) circuit in the test device is in the external test mode ( Extest mode) need to be connected to the compression circuit of the upper partition circuit. Therefore, for the design of the test device, the design of the upper-level partition circuit will be related to the structure of the isolation chain of the next-level nuclear partition circuit. Once the structure of the isolation chain in the nuclear partition circuit changes, the corresponding upper The design of the compression circuit structure of the first-level partition circuit will also be affected. [0003] Since the design of the upper-level partition circuit always...

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Problems solved by technology

Therefore, for the design of the test device, the design of the upper-level partition circuit will be related to the structure of the isolation chain of the next-level nuclear partition circuit. Once the structure of the isolation chain in the nuclear partition circuit changes, the corresponding upper The design of the compression circuit structure of the first-level partition circuit will also be affected

[0003] Since the design of the upper-level partition circuit always needs to consider the structure of the isolation chain of the next-level core partition circuit, and after the structure of each core scan chain changes, the compression circuit structure of the upper-level partition circuit must also be Follow changes, which will increase the complexity and inconvenience of circuit design

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