Methods of forming microelectronic devices, and related microelectronic devices and electronic systems

Abstract

The application relates to METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS. A method of forming a microelectronic device comprises forming a stack structure comprising vertically alternating insulating structures and additional insulating structures arranged in tiers. Each of the tiers individually comprises one of the insulating structures and one of the additional insulating structures. A first trench is formed to partially vertically extend through the stack structure. The first trench comprises a first portion having a first width, anda second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the first trench. The dielectric structure comprises a substantially void-free section proximate the horizontal boundary of the first portion of the trench. Microelectronic devices and electronic systems are also described.

Description

[0001] priority claim [0002] This application claims U.S. Patent Application Serial No. 16 filed on August 5, 2019 for "Methods of Forming Microelectronic Devices, and Related Microelectronic Devices and Electronic Systems" Priority of filing date of / 532,035. technical field [0003] The present disclosure, in various embodiments, generally relates to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to methods of forming microelectronic devices and related microelectronic devices and electronic systems. Background technique [0004] A continuing goal of the microelectronics industry is to increase the memory density (eg, the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (eg, NAND Flash devices). One way to increase memory density in non-volatile memory devices is to utilize a vertical memory array (also known as a "three-dimensional (3D) memory array") architect...

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Problems solved by technology

[0006] Unfortunately, conventional methods of forming memory devices (e.g., NAND Flash devices) have resulted in undesired current leakage (e.g., access line-to-source plate current leakage) and short circuits that may degrade the performance, reliability and durability of the desired memory device

For example, separating a preliminary stack of layers comprising an insulating structure and a further insulating structure into blocks each comprising two of the further sub-blocks is not necessary during subsequent processing of the preliminary stack (e.g., replacement of the preliminary stack with a conductive structure). During the so-called “replacement gate” or “gate last” processing) of additionally insulating one or more portions of the insulating structure to form the conductive stack structure of the memory device, undesired deposition of conductive material may result May cause undesired leakage current and short circuit

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