A ddr sending circuit

Abstract

The invention discloses a DDR sending circuit, comprising: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor, a non-inverter, an inverter and a circuit for providing a first voltage signal to the second A low-voltage device with a voltage between the three voltage signals, the source of the first PMOS transistor is connected to the third voltage signal, the gate is connected to the output end of the low-voltage device, and the drain is connected to the source of the second PMOS transistor; The three input terminals of the low-voltage device are respectively connected to the output terminal of the non-phase device, the first voltage signal and the third voltage signal; the input terminal of the non-phase device is connected to a level signal; the first NMOS transistor The source of the inverter is grounded, the gate is connected to the output terminal of the inverter, and the drain is connected to the source of the second NMOS transistor; the input terminal of the inverter is connected to the level signal; the drain of the second PMOS transistor and the second NMOS transistor The drains of the two NMOS transistors are connected to each other and connected to the first end of the resistor. The high-speed low-voltage device is used as the main drive circuit and the front drive circuit to effectively improve the working speed.

Description

technical field [0001] The invention relates to a DDR (Double Rate Synchronous Dynamic Random Access Memory) sending circuit. Background technique [0002] At present, limited by the voltage regulations in the electrical specification, the existing DDR4 and other interface transmission circuits usually still use slower high-voltage devices as the main drive circuit and front drive circuit, and it is difficult to further increase the working speed. The DDR output interface drive circuit usually uses a cmos (complementary metal oxide semiconductor) tube as the output drive resistor, or a combination of a cmos tube and a resistor to form an output drive resistor, which is limited by electrical specifications, such as the DDR4 power supply voltage is specified as 1.2v , so the main drive unit and the front drive circuit must use a high-voltage cmos tube (IO device) that can withstand more than 1.2v. With the improvement of the process, the speed of the low-voltage core device (c...

AI Technical Summary

Problems solved by technology

[0002] At present, limited by the voltage regulations in the electrical specification, the existing DDR4 and other interface transmission circuits usually still use slower high-voltage devices as the main drive circuit and front drive circuit, and it is difficult to further increase the working speed

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