One-dimensional DCT/IDCT converter for bit vector transformation accumulation shift

Abstract

The invention provides a one-dimensional DCT/IDCT converter for bit vector transformation accumulation shift. The one-dimensional DCT/IDCT converter is used for solving the problem that in an existingHEVC standard, a large number of special multipliers are used by a DCT/IDCT converter, and too many logic unit resources are occupied. The invention comprises a counting and state controller, a bit vector generator, a bit vector converter and a conversion result assembler, the counting and state controller is respectively connected with the bit vector generator, the bit vector converter and the conversion result assembler; the bit vector generator is connected with the bit vector converter, and the bit vector converter is connected with the conversion result assembler. According to the invention, the accumulation and shift combination is adopted to realize the input data multiplier, so that a large number of FPGA or ASIC logic units can be saved; because the number of clock cycles of accumulation processing is fixed and only depends on the binary complement bit number of the input data, time sequence design is easy to carry out, and DCT and IDCT can be realized in a unified structure.

Description

technical field [0001] The present invention relates to the technical field of digital video compression coding and decoding, in particular to a one-dimensional DCT / IDCT converter with bit-vector transformation, accumulation and displacement, which is used for integer approximation realized by FPGA or ASIC in High Efficiency Digital Video Coding Standard (HEVC) The discrete cosine transform / inverse discrete cosine transform (DCT / IDCT). Background technique [0002] The High Efficiency Video Coding standard (HEVC) adopts a block-based hybrid video compression coding framework, and the core transformation matrix size of the two-dimensional approximation DCT transformation specified by it is 4×4, 8×8, 16×16 and 32×32. Similarly, The core transformation matrix sizes of the two-dimensional approximate IDCT transform are 4×4, 8×8, 16×16 and 32×32. The two-dimensional transformation is separable, that is, it can be realized by performing independent one-dimensional N-point row tra...

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Problems solved by technology

However, although this scheme supports the multiplexing of smaller-sized transform blocks, it can only transform blocks of one size. When transforming small-sized blocks, the resource utilization efficiency is low.

[0006] Another main solution to reduce the number of multiplication operations is to use the even-based vector of DCT to be symmetric, and the odd-based vector to be anti-symmetrical, and use the butterfly operation to reduce the amount of arithmetic operations, especially the amount of multiplication operations, but this method cannot for IDCT transform

[0007] The existing DCT or IDCT transformation of integer approximation can be regarded as using the transformation matrix to process the input data vector, that is, in the implementation of FPGA and ASIC, the integer multiplier of the transformation matrix is ​​realized by combining shift and addition, because the transformation and The base vectors of the inverse transformation matrix have different symmetry, and only some parts of the DCT and IDCT transformations can be shared.

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