Method and circuit for pre-charging memory array and memory chip

Abstract

The embodiment of the invention provides a method and a circuit for pre-charging a memory bit line during reading operation and a memory chip, and the whole memory array can share a pre-charging circuit by adding a pre-charging bit line in the memory array to assist pre-charging, so that the cost is saved, the pre-charging speed is doubled, and the pre-charging efficiency is improved. Therefore, the reading speed is improved.

Description

technical field [0001] The various embodiments of the present application belong to the field of storage devices, and in particular relate to a method, circuit and memory chip for precharging a memory array. Background technique [0002] In the memory, precharging the bit line is a commonly used method to increase the read speed. Generally, a differential amplifier is used to generate the read result. Before the read operation is sampled, the bit line connected to the signal input terminal and the reference terminal are precharged to the power supply voltage. Half, and then turn on the memory cells on a certain row, the memory cells in different states will increase the bit line voltage or reduce the bit line voltage, and then the differential amplifier starts to sample the output results. This method is a relatively standard operation in NAND memory. [0003] In the patent No. US6175523, each column bit line has its own pre-charging circuit, which has the following defects....

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Problems solved by technology

[0003] In the patent No. US6175523, each row of bit lines has its own pre-charging circuit, which has the following defects. Each row has a pre-charging circuit, which occupies a large area of ​​the wafer and affects the cost; pre-charging is relatively slow, for NAND flash memory, because There will be a large parasitic capacitance on the bit line, and the pre-charging time often exceeds 5 microseconds, coupled with the uneven production process, often the pre-charging will be even slower

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