Overlay accuracy detection method and semiconductor structure

Abstract

The invention provides an overlay accuracy detection method and a semiconductor structure, comprising: providing a substrate, a stacked layer is formed on the substrate, a trench hole mark is formed in the stacked layer, a dielectric layer is formed in the trench hole mark, and the stacked layer A covering layer is formed on it; grooves are formed in the covering layer, and the grooves expose channel hole marks; gate line marks are formed between the channel hole marks, and the gate line marks and channel hole marks are used to detect the gate line and the channel Hole overlay accuracy. In this way, the gate line marks are formed between the channel hole marks. Since the dielectric layer is formed in the channel hole marks, the dielectric layer can support the stacked layers, thereby avoiding the grid line marks after removing the sacrificial layer in the stacked structure. There is a risk of collapse in the surrounding area, so that the overlay accuracy detection of the grid line and the via hole can be directly realized through the grid line mark and the via hole mark.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an overlay precision detection method and a semiconductor structure. Background technique [0002] Photolithography is an important step in the manufacturing process in the semiconductor field. Photolithography is the process of transferring the pattern on the mask plate to the target substrate through steps such as alignment, exposure, and development. A semiconductor product consists of multi-layer functional film layers, and multi-layer photolithography is required to complete the entire product manufacturing process. The position alignment of the current functional film layer and the previous layer of functional film layers is particularly important. Overlay testing is the key to semiconductor manufacturing. A basic process in the photolithography process, the overlay accuracy reflects the degree of alignment between different functional film layers. [0003] The ove...

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Problems solved by technology

[0004] However, in the 3D-NAND memory manufacturing process, after the step structure is formed, if a gate line mark (gate line mark) is directly formed on the stack structure, that is, an overlay accuracy detection pattern, after removing the sacrificial layer in the stack structure, the gate The area around the line mark is at risk of peeling and cannot be effectively checked for overlay accuracy

Therefore, the existing method can only indirectly judge the gate line and channel by combining the overlay accuracy of the gate line and the dummy channel hole (dummy channel hole) with the overlay accuracy of the dummy channel hole and the upper channel hole (upper channel hole). The overlay accuracy of the hole cannot be directly detected by the grid line mark and the channel hole mark

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