A processor instruction cache-oriented low-power-consumption compiling method

Abstract

The invention discloses a processor instruction cache-oriented low-power-consumption compiling method. The method comprises the following steps of S1, searching an innermost layer loop; s2, judging whether the found innermost-layer cycle can be expanded or not; s3, calculating the number of expansion times by combining with L0 cache, namely calculating the number of expansion times according to the maximum pseudo instruction number MAX-UNROLLED-INSNS of the loop body, the maximum average pseudo instruction number MAX-AVERAGE-UNROLLED-INSNS of the loop body and the maximum number of expansion times MAX-UNROLL-TIMES; s4, realizing code expansion according to the expansion times; s5, establishing a dependency graph for the statements in the loop at the middle end of the compiler, and settingeach statement in the loop as an area; s6, traversing all regions, and checking whether a dependency relationship of producers and consumers exists or not; s7, determining the optimal partition size according to the L0 cache capacity; s8, selectively merging the statements; and S9, generating a cyclic tree for each of the remaining partitions to realize cyclic stripping. According to the invention, a loop-optimized fine control strategy is realized, the high hit rate of the L0 cache is ensured, and the power consumption of instruction fetching and decoding is effectively reduced, so that the performance is improved and the power consumption is reduced.

Description

Technical field [0001] The present invention relates to a low power compilation method for processor instruction cache, belonging to the technical field of computer. Background technique [0002] Usually the access amount of the Cache (I-Cache) is much larger than the data cache (d-cache), so the power consumption of I-Cache occupies the main part of the CPU power consumption. L0 Cache is an increase in instruction Cache structure between L1 i-cache and water, mainly compared with traditional Cache, mainly below: First, L0 Cache is stored in decoding instructions, reducing decoding Time, improved CPU actual efficiency; second, L0 Cache capacity is small, small area, reduced static power consumption; third, the instruction stream has better space, time, even if the capacity is small L0 Cache also has a relatively high hit rate, reducing dynamic power consumption; fourth, when the CPU accesses L0 Cache, it is not necessary to compare the marker domain and data domain of each of the...

AI Technical Summary

Problems solved by technology

However, the traditional compiler optimization algorithm for loop compilation often considers a single performance index, lacks low-power compilation optimization technology for instruction cache, and cannot efficiently use instruction cache components

At the same time, the adaptive adjustment of optimization parameters is not made according to the hardware structure characteristics of the L0 cache, and the high hit rate of the L0 cache cannot be effectively guaranteed.

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