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I2C slave circuit based on SCL real-time high-level pulse width

A high-level, pulse-width technology, applied in electrical digital data processing, instruments, energy-saving calculations, etc., can solve problems such as inability to support high-frequency and high-data-bandwidth I2C communications, and increase chip power consumption.

Pending Publication Date: 2021-03-09
HENGXIN SEMITECH CO LTD
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Problems solved by technology

[0010] On the one hand, increasing the operating clock frequency means increasing the power consumption of the chip. On the other hand, if the chip cannot provide a higher frequency operating clock to the I2C slave circuit, the I2C slave circuit will not be able to support the high High frequency data bandwidth I2C communication

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  • I2C slave circuit based on SCL real-time high-level pulse width
  • I2C slave circuit based on SCL real-time high-level pulse width
  • I2C slave circuit based on SCL real-time high-level pulse width

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Embodiment Construction

[0039] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and implement it, but the examples given are not intended to limit the present invention.

[0040] refer to figure 1 Shown, an embodiment of the I2C slave circuit based on SCL real-time high level pulse width of the present invention, comprises synchronization and judgment circuit module and I2C slave state machine module, described synchronization and judgment circuit module and I2C slave state Between the machine modules, there are functional modules for detecting the real-time high-level pulse width of SCL and predicting the time of SCL falling edge. The functional module for detecting the real-time high-level pulse width of SCL and predicting the moment of SCL falling Notify the I2C slave state machine module of the falling edge position of SCL.

[0041] The princi...

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Abstract

The invention discloses an I2C slave circuit based on SCL real-time high-level pulse width, which comprises a synchronization and judgment circuit module and an I2C slave state machine module, and a function module for detecting SCL real-time high-level pulse width and predicting SCL falling edge time is arranged between the synchronization and judgment circuit module and the I2C slave state machine module. The function module for detecting the SCL real-time high-level pulse width and predicting the SCL falling edge moment can predict the SCL falling edge position and inform the I2C slave state machine module of the predicted SCL falling edge position. On one hand, the I2C slave circuit can complete higher-frequency and higher-bandwidth I2C communication under the existing working clock frequency; and on the other hand, the power consumption of the chip can be effectively reduced by lowering the working clock frequency of the I2C slave circuit.

Description

technical field [0001] The invention relates to the field of I2C slave circuits, in particular to an I2C slave circuit based on SCL real-time high-level pulse width. Background technique [0002] The I2C bus is a simple, two-way two-wire synchronous serial bus developed by Philips. It requires only two wires (SCL and SDA) to transfer information between devices connected to the bus. [0003] In the I2C bus, SCL is the clock line, generally initiated by the master, and the slave is responsible for receiving. [0004] In the I2C bus, SDA is a data line, and both the master and the slave will send information to each other through SDA. The host and slave will not send data on SDA at the same time, usually according to the timing specified in the I2C protocol, the host and slave will select the appropriate time to send data to SDA. [0005] According to the I2C protocol, no matter the host or the slave, when you want to send information on SDA, you must comply with the SCL lo...

Claims

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Application Information

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IPC IPC(8): G06F13/42
CPCG06F13/4291G06F2213/0016Y02D10/00
Inventor 卓越朱建银
Owner HENGXIN SEMITECH CO LTD
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