Slave core software cache sharing method for many-core processor

A technology of many-core processors and software, applied in the field of data sharing for slave-core software cache, can solve the problems of software cache without consistency guarantee and reduce program programmability, so as to ensure data consistency and reduce delay. , to avoid cumbersome effects

Pending Publication Date: 2021-03-09
BEIHANG UNIV
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  • Slave core software cache sharing method for many-core processor
  • Slave core software cache sharing method for many-core processor
  • Slave core software cache sharing method for many-core processor

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[0050] In order to make the purpose, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific examples described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not constitute a conflict with each other.

[0051] The new APIs required by the present invention are shown in Table 1.

[0052] The hardware architecture diagram of the present invention is as follows figure 1 As shown, here is a description of the slave core array of a core group. The task division and communication process are as follows figure 2 shown.

[0053] The specific implementation steps of the present invention are as follow...

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Abstract

The invention discloses a slave core software cache sharing method for a many-core processor, and the method comprises the steps: 1), reasonably dividing a slave core into a calculation core, a routing core and a management core, and enabling different types of cores to undertake different tasks; 2) managing the data according to pages, and supporting conversion between a main memory global address and a software cache local address; 3) during operation, through detection, data in the core software cache being automatically exchanged in and out, and manual control of a user not being needed; 4) a cache consistency protocol suitable for SW 26010 slave cores of a many-core processor being provided, and the problem of data consistency between slave core software caches being solved; and 5) the protocol, the lock and the fence operation primitive of Shenwei SW26010 slave inter-core register communication based on the many-core processor being realized. According to the invention, the sharing of the slave core software cache is realized, the cumbersome operation of manually managing the software cache is avoided, and the development efficiency of the software on the many-core processorSW SW26010 is further improved.

Description

technical field [0001] The invention relates to the fields of parallel software development based on the many-core processor Shenwei SW26010, slave core software cache management, slave core software cache consistency, etc., and in particular relates to a data sharing method for slave core software cache. Background technique [0002] Shenwei SW26010 processor is the first self-developed many-core processor in my country, which adopts an on-chip fusion heterogeneous many-core architecture. This processor contains four core groups (Core Groups, referred to as CGs), each core group has a master core (MPE) and an 8*8 slave core (Computing Processing Elements, referred to as CPEs)) array. Each core group has a memory controller (MC for short), and each core group also has an independent memory space, and the connection between the core group and the memory depends on the memory controller allocated by the core group. [0003] In addition, each main core (MPE) has a 32KB instruc...

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Application Information

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IPC IPC(8): G06F15/167G06F9/52
CPCG06F15/167G06F9/52Y02D10/00
Inventor 杨海龙陈邦铎敦明
Owner BEIHANG UNIV
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