Three-dimensional memory structure and its preparation method
A memory, three-dimensional technology, applied in the direction of semiconductor devices, electric solid devices, electrical components, etc., can solve the problems of difficult to effectively disperse stress, limited zoning of step areas, etc., to achieve the effect of stress dispersion
Active Publication Date: 2022-05-17
YANGTZE MEMORY TECH CO LTD
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Problems solved by technology
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory structure and its preparation method, which are used to solve the problems in the prior art, such as the limited division of the step area and the difficulty in effectively dispersing the stress.
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preparation example Construction
[0066] Such as figure 1 As shown, the present invention provides a preparation method of a three-dimensional memory structure, the preparation method comprising the following steps:
[0067] S1, providing a semiconductor substrate;
[0068] S2, forming a stacked structure on the semiconductor substrate, the stacked structure including adjacent core regions and step regions;
[0069] S3, etching the step area to form N sub-step areas, and each of the sub-step areas is arranged around a step center, wherein, for each of the sub-step areas, several steps of different stages are formed , the N sub-step regions form M series steps, N is an integer greater than or equal to 3, and M is an integer greater than or equal to 3;
[0070] Wherein, the step region is further formed with a bridging region to realize the electrical connection between each of the sub-step regions and the core region.
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The invention provides a three-dimensional memory structure and a preparation method thereof. The preparation includes: forming a stacked structure on a semiconductor substrate, the stacked structure includes a core area and a step area, etching the step area to form N sub-step areas, and each The sub-step areas are arranged around the center of a step, and the N sub-step areas form M series of steps, where N and M are both integers greater than or equal to 3. In addition, a bridging area is formed in the step area. The three-dimensional memory structure and its preparation method of the present invention can make the step area into steps of at least three partitions, and the steps can be made into circular steps, each circle of steps corresponds to different partitions, and the design of the steps can be used in different The sub-step area arranged around the center of the step is conducive to stress dispersion; in addition, the bridge junction area can be effectively formed in the step etching to realize the electrical connection between the step area and the core area.
Description
technical field [0001] The invention belongs to the field of semiconductor design and manufacture, and in particular relates to a three-dimensional memory structure and a preparation method thereof. Background technique [0002] In the chip manufacturing process, the silicon substrate (Si Substrate) is used as the carrier for making the chip. As the number of chip layers increases, more dielectric films are needed, such as TEOS (tetraethoxysilane), SIN (silicon nitride ), POLY (polysilicon). For example, SS (step area), CH (channel hole structure), and GL Area (gate gap area) in 3D NAND need to be filled with more dielectrics, and at the same time, the thin film structure will become longer and more complicated. In addition, after the heat treatment in the process, the film will be deformed, and the silicon substrate is difficult to support the wafer deformation caused by the stress of the film, which will eventually cause the wafer to deform (arcing) or cannot be processed...
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IPC IPC(8): H01L27/11565H01L27/1157H01L27/11582
CPCH10B43/10H10B43/35H10B43/27
Inventor 张坤孔翠翠张中周文犀吴林春
Owner YANGTZE MEMORY TECH CO LTD