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SON structure and preparation method thereof

A combined structure and trench technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve problems such as the influence of device structure

Active Publication Date: 2021-04-23
上海烨映微电子科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above-mentioned shortcoming of the prior art, the purpose of the present invention is to provide a kind of SON structure and preparation method thereof, be used to solve the SON preparation process in the prior art Influence of bonding on device structure and other issues

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  • SON structure and preparation method thereof
  • SON structure and preparation method thereof

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Embodiment Construction

[0052]Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth shou...

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Abstract

The invention provides an SON structure and a preparation method thereof. The preparation method comprises the following steps of: providing a first semiconductor substrate; forming an intermediate oxide layer on the first semiconductor substrate; preparing a trench combination structure comprising a first trench, a second trench and an annular third trench in the intermediate oxide layer, the second trench being communicated with the first trench and comprising a unit row extending to the end part of the intermediate oxide layer; forming a defect layer in a second semiconductor substrate; bonding the second semiconductor substrate with the intermediate oxide layer; and stripping the second semiconductor substrate from the defect layer. The invention provides a method for preparing SON in a non-vacuum manner. The trench combination structure is prepared in the intermediate oxide layer formed by an oxidation process, and through the combination of the first trench, the second trench and the third trench, a window pattern in a cavity structure is connected with a circular ring trench through strip-shaped trenches, a certain number of strip-shaped trenches extend to the edge of a silicon wafer, so that the structure is communicated with external air, the consistency of internal and external pressures is ensured, and meanwhile, the problem of mechanical strength caused by heating expansion of gas in a cavity and vacuum is solved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device structure design and manufacture, and in particular relates to a SON structure and a preparation method. Background technique [0002] SON (Silicon on Nothing) is a material similar to silicon on insulator (SOI). There are holes between the top silicon and the substrate silicon. The existence of this hole layer makes SON materials have some unique advantages. [0003] Compared with SOI materials, the SON structure can further reduce the coupling from the drain terminal to the source terminal through the buried oxide layer, effectively suppress the DIBL effect, and improve the performance of the device. Reducing the coupling effect through BOX can reduce the minimum channel length of transistors, so that MOSFETs based on SON materials can be applied to lower technology nodes. Due to the embedded so-called "void" (vacuum or air) layer under the Si film has a lower dielectric constant t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L21/762
CPCH01L27/1203H01L21/76254
Inventor 张洋徐德辉荆二荣
Owner 上海烨映微电子科技股份有限公司
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