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Son structure and its preparation method

A combined structure and trench technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as the influence of device structure, and achieve the effect of ensuring internal and external pressure and solving mechanical strength problems.

Active Publication Date: 2022-04-19
上海烨映微电子科技股份有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the above-mentioned shortcoming of the prior art, the purpose of the present invention is to provide a kind of SON structure and preparation method thereof, be used to solve the SON preparation process in the prior art Influence of bonding on device structure and other issues

Method used

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  • Son structure and its preparation method

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Embodiment Construction

[0052]Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] For example, when describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, which should not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth shou...

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Abstract

The invention provides a SON structure and a preparation method thereof. The preparation method includes: providing a first semiconductor substrate; forming an intermediate oxide layer on the first semiconductor substrate; A groove combination structure of a groove and an annular third groove, the second groove communicates with the first groove and includes a cell row extending to the end of the middle oxide layer; a defect layer is formed in the second semiconductor substrate; bonding the second semiconductor substrate to the middle oxide layer; peeling off the second semiconductor substrate from the defect layer. The invention provides a method for preparing SON in a non-vacuum state. A groove combination structure is prepared in the intermediate oxide layer formed by an oxidation process. The combination of the first groove, the second groove and the third groove is equivalent to a cavity structure. The middle window pattern is connected with the ring groove through strip grooves, and a certain number of strip grooves extend to the edge of the silicon wafer to communicate with the outside air to ensure consistent internal and external pressure, and at the same time solve the problem of gas pressure in the cavity. Thermal expansion and vacuum cause mechanical strength problems.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device structure design and manufacture, and in particular relates to a SON structure and a preparation method. Background technique [0002] SON (Silicon on Nothing) is a material similar to silicon on insulator (SOI). There are holes between the top silicon and the substrate silicon. The existence of this hole layer makes SON materials have some unique advantages. [0003] Compared with SOI materials, the SON structure can further reduce the coupling from the drain terminal to the source terminal through the buried oxide layer, effectively suppress the DIBL effect, and improve the performance of the device. Reducing the coupling effect through BOX can reduce the minimum channel length of transistors, so that MOSFETs based on SON materials can be applied to lower technology nodes. Due to the embedded so-called "void" (vacuum or air) layer under the Si film has a lower dielectric constant t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/12H01L21/762
CPCH01L27/1203H01L21/76254
Inventor 张洋徐德辉荆二荣
Owner 上海烨映微电子科技股份有限公司
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