Software-defined on-chip system, data interaction method and system architecture

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a software-defined on-chip system, a data interaction method and a system architecture, the system comprises a wafer-level interconnection substrate, a plurality of prefabricated members arranged on the wafer-level interconnection substrate, and a software-defined on-chip interconnection network used for interconnection among different prefabricated members, each prefabricated member is integrated with different function calculation particles according to field application function requirements; the prefabricated members follow a unified interface standard and a physical layer protocol specification, and data exchange is carried out between the prefabricated members through a wafer-level interconnection substrate and a software-defined on-chip interconnection network, so that different function calculation particles are recombined and/or rebuilt in a software-defined mode to adapt to different application requirements and task mapping requirements. According to the method, boundary conditions such as a design method, a calculation normal form, an implementation material and an integration mode of an existing integrated circuit are broken through, and flexible interconnection and functional reconstruction of different prefabricated members for field application are realized, so that complex and diversified application task requirements are met.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and in particular relates to a software-defined on-chip system, a data interaction method, and a system architecture. Background technique [0002] With the gradual failure of Moore's Law and Dennard's scaling law, the traditional engineering technology route based on the layer-by-layer stacking system of devices, components, modules, and racks has encountered a sustainable development bottleneck. At present, the chip process is getting closer and closer to the quantum effect area, the number of transistors per unit area is increasing, the yield control is becoming more and more difficult, the problem of power consumption is becoming more and more prominent, and the manufacturing and design costs are rising exponentially. Single-chip performance improvement has approached the ceiling. At the same time, when continuing to use the traditional engineering technology route of "stacking" devic...

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Problems solved by technology

[0003] Since different types of application tasks have different computing characteristics, the requirements for computing-storage-communication resources are also different, and multiple types of parallelism, different limitations, and different communication and synchronization requirements may be mixed within application tasks. The computing performance of the same application on different architectures will vary greatly. Therefore, it is necessary for the application to adapt to the solidified system structure from the perspective of function and performance. The flexibility and scalability are poor and have great limitations. Application performance It will also be greatly reduced, and it is difficult to meet the complex and diverse application task requirements

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