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Access line management for an array of memory cells

A technology of memory unit and access line, which is applied in the direction of static memory, digital memory information, information storage, etc.

Pending Publication Date: 2021-06-11
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

FeRAM can use a device architecture similar to volatile memory, but may have non-volatile properties due to the use of ferroelectric capacitors as storage devices

Method used

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  • Access line management for an array of memory cells
  • Access line management for an array of memory cells
  • Access line management for an array of memory cells

Examples

Experimental program
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Embodiment Construction

[0023] Some memory arrays can include a panel common to multiple memory cells, and the memory cells are also associated with multiple digital lines and / or multiple word lines. Since the voltage of the board (and thus is also the voltage of the associated cable line) is fluctuating related to the access operation of the memory cell (eg, between the high voltage and the low voltage), some memory devices can be used For each word line of the co-panel, each word line (which can be referred to as an unselected word line) is maintained at a fixed voltage. This may be attributed to capacitance (e.g., parasitic) cross-coupling associated with each unselected word line (eg, between each unselected word line and common panel or board line), resulting in leakage current and related Global loss. In the case of a multi-memory cell, the amount of capacitance between the board and the unselected word line and the non-expected cross-coupling may be significant, and therefore, the amount of asso...

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Abstract

Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and / or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and / or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.

Description

[0001] cross reference [0002] This patent application requests Vimercati's priority to US patent application, filed on November 26, 2019, is the priority of US patent application, which is Vimercati on May 4, 2018. Submitted the title of "Access Line Management for An Arrayof Memory Cells", and each application is transferred to this accusation. It is incorporated herein by reference in its entirety. Technical field [0003] The technical field involves access line management of memory cell arrays. Background technique [0004] The following content generally involves managing access to memory cells, and more specifically, involving access line management for memory cell arrays. [0005] The memory device is widely used to store information in various electronic devices such as a computer, a wireless communication device, a camera, a digital display, and a similar person. Information is stored in different states of programming memory devices. For example, the binary device has...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/4063G11C11/408G11C11/409G11C11/4094
CPCG11C11/4063G11C11/4094G11C11/409G11C11/4085Y02D10/00G11C11/2259G11C11/221G11C11/2257G11C8/08
Inventor D·维梅尔卡蒂
Owner MICRON TECH INC