Storage controller for correcting error, storage device including same, and operating method thereof

Abstract

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2019-0164302 filed on December 11, 2019 at the Korean Intellectual Property Office and U.S. Patent Application No. 16 / 917,101 filed on June 30, 2020 at the USPTO , the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] Apparatus, devices, and methods consistent with the present disclosure relate to semiconductor memory, and more particularly, to a memory controller for error correction, a memory device including the memory controller, and an operating method thereof. Background technique [0004] A semiconductor memory supports a write operation for storing data and a read operation for reading stored data. Errors may occur when data is written in the semiconductor memory, when data is stored in the semiconductor memory, or when data is read from the semiconductor memory. This error can be corrected by ...

AI Technical Summary

Problems solved by technology

However, in the case of implementing multiple error handling devices for each of multiple semiconductor memories to cope with both scenarios, the chip area may increase, or the throughput may decrease in certain cases

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