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Storage controller for correcting error, storage device including same, and operating method thereof

A memory controller, memory technology, used in static memory, instrumentation, error detection/correction, etc., to solve problems such as reduced throughput and increased chip area

Pending Publication Date: 2021-06-11
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the case of implementing multiple error handling devices for each of multiple semiconductor memories to cope with both scenarios, the chip area may increase, or the throughput may decrease in certain cases

Method used

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  • Storage controller for correcting error, storage device including same, and operating method thereof
  • Storage controller for correcting error, storage device including same, and operating method thereof
  • Storage controller for correcting error, storage device including same, and operating method thereof

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Embodiment Construction

[0034] Hereinafter, various exemplary embodiments may be described in detail and clearly so that those of ordinary skill in the art can easily implement the various exemplary embodiments. The terms 'unit', 'module', etc. used in the specification may be implemented in the form of hardware, software, or a combination thereof configured to perform various functions to be described in the specification.

[0035] figure 1 is a block diagram illustrating a storage system according to an exemplary embodiment. refer to figure 1 , the storage system 100 may include a host 110 and a storage device 1000 . In an exemplary embodiment, storage system 100 may be a computing system configured to process various information, such as a personal computer (PC), notebook computer, laptop computer, server, workstation, tablet PC, smartphone, digital camera or black box.

[0036] The host 110 may control the overall operation of the storage system 100 . For example, the host 110 may store data...

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Abstract

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to Korean Patent Application No. 10-2019-0164302 filed on December 11, 2019 at the Korean Intellectual Property Office and U.S. Patent Application No. 16 / 917,101 filed on June 30, 2020 at the USPTO , the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] Apparatus, devices, and methods consistent with the present disclosure relate to semiconductor memory, and more particularly, to a memory controller for error correction, a memory device including the memory controller, and an operating method thereof. Background technique [0004] A semiconductor memory supports a write operation for storing data and a read operation for reading stored data. Errors may occur when data is written in the semiconductor memory, when data is stored in the semiconductor memory, or when data is read from the semiconductor memory. This error can be corrected by ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42
CPCG11C29/42G06F11/1048
Inventor 郭熙烈张宰薰孙弘乐申东旻柳根荣李冈石韩泫昇
Owner SAMSUNG ELECTRONICS CO LTD