Semiconductor structure and its preparation method

Abstract

The present invention relates to a semiconductor structure and a preparation method thereof, comprising: providing a substrate; forming a gate trench in the substrate, the gate trench including a first trench and a second trench; the first trench The second trench is located above the first trench and communicates with the first trench, the width of the second trench is greater than the width of the first trench; formed in the gate trench gate word line. The preparation method of the semiconductor structure of the present invention can obtain a gate word line with a wider upper part by preparing a gate trench whose upper part is wider than the lower part. Since the upper part of the gate word line is wider, it is convenient for the first interconnection structure to connect with the gate trench. The alignment contact of the word line can ensure that the first interconnection structure and the gate word line have a sufficiently large contact area, thereby reducing the contact resistance between the first interconnection structure and the gate word line, and improving the electrical properties of the storage device. The storage device has better reading and writing speed and storage efficiency.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a semiconductor structure and a preparation method thereof. Background technique [0002] The development of dynamic memory pursues high speed, high integration density, and low power consumption. With the shrinking of the structure size of semiconductor devices, especially in the DRAM manufacturing process with critical dimensions less than 20nm, the size of the gate word line shrinks, and the contact resistance between the gate word line and the conductive interconnect structure directly determines the electrical properties of the DRAM. The resistance value of the connection directly determines the current level and signal delay time; especially for the gate word line, the size and stability of the current signal directly determine the storage speed and storage efficiency of the device. [0003] However, in the prior art, the width of the top of the gate wo...

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Problems solved by technology

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof in order to solve the above-mentioned problems, so as to solve the problem that the interconnection structure is biased compared with the gate word line in the prior art due to the small width of the top of the gate word line. shift, so that the contact area between the two is small, which leads to the problem of high contact resistance between the interconnect structure and the gate word line

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