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Stacked semiconductor device and test method thereof

A technology for semiconductors and devices, applied in the field of testing of stacked semiconductor devices, can solve problems such as inability to electrically connect multiple chips

Pending Publication Date: 2021-07-09
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Faulty TSVs fail to electrically connect multiple chips

Method used

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  • Stacked semiconductor device and test method thereof
  • Stacked semiconductor device and test method thereof
  • Stacked semiconductor device and test method thereof

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Embodiment Construction

[0040] Various embodiments of the invention will be described in more detail below with reference to the accompanying drawings. However, this invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts in the various figures and embodiments of the invention. It should also be noted that in this specification, "connected / coupled" not only means that one component is directly coupled with another component but also indirectly couples with another component through an intermediate component. Also, a singular form may include a plural form if not specifically mentioned in the sentence.

[0041]Hereinafter, a semiconductor memory system will be described taking a stacked semicondu...

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Abstract

A stacked semiconductor device and a test method thereof are disclosed. The semiconductor device includes a forcing line extending in a first direction over a through-electrode, and electrically coupled to the through-electrode; a first monitoring line formed separate from the forcing line by a first interval in a second direction, and extended in the first direction; a second monitoring line formed separate from the forcing line by a second interval in an opposite direction to the second direction, and extended in the first direction; and a selection circuit suitable for outputting a detection signal by selecting any one of a plurality of voltage levels of the first and second monitoring lines according to a monitoring signal.

Description

[0001] Cross References to Related Applications [0002] This application claims Korean Patent Application No. 10-2019-0173005 filed on December 23, 2019, Korean Patent Application No. 10-2019-0174014 filed on December 24, 2019, and February 2020 Priority of Korean Patent Application No. 10-2020-0016383 filed on the 11th, the entire contents of which are hereby incorporated by reference. technical field [0003] Various embodiments of the invention relate generally to semiconductor design techniques, and more particularly, to testing methods for stacked semiconductor devices. Background technique [0004] With the rapid development of semiconductor technology, packaging technology for semiconductor integrated devices requires high integration and high performance. Therefore, in addition to a two-dimensional (2D) structure in which a semiconductor chip having an integrated circuit formed therein is two-dimensionally arranged on a printed circuit board (PCB) through wires or ...

Claims

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Application Information

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IPC IPC(8): H01L23/544H01L21/66H01L25/18
CPCH01L22/32H01L22/34H01L25/18
Inventor 吴相默金支焕李东郁李康说张宪龙
Owner SK HYNIX INC