Check patentability & draft patents in minutes with Patsnap Eureka AI!

AS6802 synchronization frame transparent transmission system and method in TTE switch

An AS6802, transparent transmission technology, applied in the field of AS6802 synchronous frame transparent transmission system, can solve the problems of increased delay, inability to synchronize, and reduced network efficiency, and achieves the reduction of transmission delay, avoidance of data loss, and avoidance of forwarding delay. Effect

Active Publication Date: 2021-07-13
XIDIAN UNIV
View PDF13 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this method is that since this method does not involve the transparent transmission of synchronization frames, it can only be used for clock synchronization of a network with a single switching device, and is not suitable for clock synchronization of a network of multiple switching devices. Form a large-scale time-triggered Ethernet system
The disadvantage of this method is that, first, when the switch forwards, the synchronization frame is treated as an ordinary Ethernet frame, and the priority of the synchronization frame is lower than that of the TT service frame, which causes the transmission delay of the synchronization frame to increase and crowds the TT of the switch. The transmission bandwidth of the business, especially the transmission bandwidth occupied by multi-level cascading, will be unbearable; second, the synchronization frame switching plane is specially set up to separate the time synchronization unit from the transparent transmission of the synchronization frame, which wastes logical resources and must be static Configuring the switching path greatly reduces the flexibility and greatly increases the delay; third, the forwarding delay of the synchronization frame does not take into account the PHY delay of the board, and the synchronization accuracy cannot be guaranteed, especially when multi-level cascading may cause synchronization failure; Fourth, the priority of the synchronization frame is not set to the highest priority, which will cause the device to fail to synchronize in high-density business transmission
[0006] (1) The existing AS6802 standard-based switching device clock synchronization method does not involve the transparent transmission of synchronization frames, so it can only be used for clock synchronization of a network with a single switching device, and is not suitable for clock synchronization of a network of multiple switching devices , cannot constitute a large-scale time-triggered Ethernet system
[0007] (2) In the prior art, when the switch forwards, the synchronization frame is treated as an ordinary Ethernet frame, and the priority of the synchronization frame is lower than that of the TT service frame, resulting in an increase in the transmission delay of the synchronization frame, and crowding out the transmission of the TT service of the switch Bandwidth, especially the transmission bandwidth occupied by multi-level cascading will be unbearable
[0008] (3) Existing Ethernet switches specially set up a synchronization frame switching plane to separate the time synchronization unit from the transparent transmission of the synchronization frame, which wastes logical resources and must also statically configure the switching path, greatly reducing flexibility and greatly increasing delay
[0009] (4) In the prior art, the forwarding delay of the synchronization frame does not consider the PHY delay of the board, and the synchronization accuracy cannot be guaranteed, especially when multi-level cascading may cause synchronization failure; meanwhile, the priority of the synchronization frame is not set to The highest priority, which will cause the device to fail to synchronize during high-density business transmission
In the existing technology, when the switch forwards, the synchronization frame is treated as an ordinary Ethernet frame, which not only does not comply with the AS6802 standard, but also greatly increases the transmission delay of the synchronization frame, which affects the synchronization accuracy and even causes the problem of synchronization failure
The difficulty to solve is not only to ensure the function and performance requirements of synchronization, but also to ensure the available bandwidth of TT services as much as possible, because the purpose of synchronization is for the transmission of TT services. If the synchronization process occupies too much bandwidth, it will make the entire network Reduced efficiency

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • AS6802 synchronization frame transparent transmission system and method in TTE switch
  • AS6802 synchronization frame transparent transmission system and method in TTE switch
  • AS6802 synchronization frame transparent transmission system and method in TTE switch

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0131] The purpose of the present invention is to provide a device and method for transparent transmission of AS6802 synchronous frames in a TTE exchange for the deficiencies of the prior art.

[0132] In order to achieve the above object, the idea of ​​the present invention is: the programmable logic chip FPGA realizes a multi-port time-triggered Ethernet switch, and the device is mainly used for the transparent transmission of the AS6802 synchronization frame in the TTE network. Listen to the synchronization frame passing through each port of the switch to obtain the receiving time point, and analyze the received synchronization frame to obtain all frame information of the synchronization frame, including: destination address, source address, integration period, member vector, Synchronization priority, synchronization domain, frame type, and transparent clock value, store all frame information in registers. Then identify the identification bit of the cascading port, synthesi...

Embodiment 2

[0164] The transparent transmission method of AS6802 synchronous frame in the TTE exchange that the embodiment of the present invention provides, comprises the following steps:

[0165] (1) Configure the state of the cascading port flag bit of the TTE switch port:

[0166] Assume that the TTE switch includes P ports, one of which is a cascading port, and the remaining P-1 ports are non-cascading ports, the flag bit of the cascading port is in a valid state, and the flag bit of a non-cascading port is in an invalid state, where P≥2;

[0167] (2) Receive the first-in-first-out queue FIFO module to obtain the correct AS6802 synchronization frame and cache it:

[0168] (2a) the synchronous frame receiving module receives N continuous AS6802 synchronous frame A that TTE switchboard input distribution module outputs, A={A i}, where A i Indicates the i-th AS6802 synchronization frame, i∈[1,N], N≥2;

[0169] (2b) The cyclic redundancy check module is to each A received by the sync...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention belongs to the technical field of communication, and discloses an AS6802 synchronization frame transparent transmission system and method in a TTE switch, and the AS6802 synchronization frame transparent transmission system in the TTE switch comprises a receiving first-in first-out queue FIFO module, a receiving interception module, a frame analysis module, a frame information cache management module, a synchronization frame transparent transmission management module, and a sending first-in first-out queue FIFO module. The AS6802 synchronous frame transparent transmission method in the TTE switch comprises the steps of synchronous frame caching, interception receiving time and frame analysis, frame information and receiving time point cache management, whether a synchronous frame transparent transmission management module is idle or not, synchronous frame synthesis, synchronous frame sending and synchronous frame arbitration. According to the method, the problem of transparent transmission of the synchronization frame is solved, the number of nodes which can be supported by the TTE system is increased, the residence time and the maximum transmission delay of the system synchronization frame are reduced, and the adaptability and the clock synchronization precision of the TTE switch are improved.

Description

technical field [0001] The invention belongs to the technical field of communication, and in particular relates to a transparent transmission system and method of an AS6802 synchronization frame in a TTE switch. Background technique [0002] At present, with the rapid development of science and technology, the modern industrial control system is becoming larger and larger, and the high-precision and high-reliability synchronous Ethernet switching network composed of a single switching device is increasingly unable to meet the demand. The high-accuracy, high-reliability synchronous Ethernet switching network is more and more concerned. The SAE AS6802 standard defines time-triggered services for Ethernet networks, providing high-precision, high-reliability, and fault-tolerant precise clock synchronization for time-triggered Ethernet. Implementing the synchronization client function component defined by AS6802 synchronization in the TTE switch can realize the cascaded clock sy...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04L12/861H04L12/935H04L7/00H04L49/111
CPCH04L49/30H04L49/90H04L7/0033
Inventor 邱智亮曹家亮潘伟涛楼耀琛张洪斌狄昕涛董勐
Owner XIDIAN UNIV
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More