AS6802 synchronization frame transparent transmission system and method in TTE switch
An AS6802, transparent transmission technology, applied in the field of AS6802 synchronous frame transparent transmission system, can solve the problems of increased delay, inability to synchronize, and reduced network efficiency, and achieves the reduction of transmission delay, avoidance of data loss, and avoidance of forwarding delay. Effect
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Embodiment 1
[0131] The purpose of the present invention is to provide a device and method for transparent transmission of AS6802 synchronous frames in a TTE exchange for the deficiencies of the prior art.
[0132] In order to achieve the above object, the idea of the present invention is: the programmable logic chip FPGA realizes a multi-port time-triggered Ethernet switch, and the device is mainly used for the transparent transmission of the AS6802 synchronization frame in the TTE network. Listen to the synchronization frame passing through each port of the switch to obtain the receiving time point, and analyze the received synchronization frame to obtain all frame information of the synchronization frame, including: destination address, source address, integration period, member vector, Synchronization priority, synchronization domain, frame type, and transparent clock value, store all frame information in registers. Then identify the identification bit of the cascading port, synthesi...
Embodiment 2
[0164] The transparent transmission method of AS6802 synchronous frame in the TTE exchange that the embodiment of the present invention provides, comprises the following steps:
[0165] (1) Configure the state of the cascading port flag bit of the TTE switch port:
[0166] Assume that the TTE switch includes P ports, one of which is a cascading port, and the remaining P-1 ports are non-cascading ports, the flag bit of the cascading port is in a valid state, and the flag bit of a non-cascading port is in an invalid state, where P≥2;
[0167] (2) Receive the first-in-first-out queue FIFO module to obtain the correct AS6802 synchronization frame and cache it:
[0168] (2a) the synchronous frame receiving module receives N continuous AS6802 synchronous frame A that TTE switchboard input distribution module outputs, A={A i}, where A i Indicates the i-th AS6802 synchronization frame, i∈[1,N], N≥2;
[0169] (2b) The cyclic redundancy check module is to each A received by the sync...
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