Method and system for preventing chip from entering test mode by mistake
A test mode and chip technology, which is applied in the direction of electronic circuit testing, measuring electricity, measuring devices, etc., can solve problems such as safety problems, chips entering the test mode by mistake, and chips not working properly, etc.
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[0087] This embodiment is an embodiment of a specific application of the system for preventing the chip from accidentally entering the test mode, where the effective level is 0 level.
[0088] The preset module presets the imported pattern corresponding to the test mode. The data structure of the imported pattern can include 18 bytes of data, among which, the 0th to 15th bytes can correspond to the imported part, which can be "01011001_01010100", The 16th to 17th bytes can correspond to the configuration part in the signal, as shown in Table 1 below:
[0089]
[0090] Table 1
[0091] The reset pin of the chip receives the first signal Reset_n, the clock pin receives the clock signal test_clock, the debounce unit in the control module performs debounce processing on the first signal Reset_n, and generates the second signal Internal_reset_n, and the control unit generates the second signal Internal_reset_n according to the first signal Reset_n, The clock signal test_clock a...
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